Skyworks Solutions Inc. SI5394J-A-GMR

Overview

SI5394J-A-GMR from Skyworks Solutions is a 4-input, 4-output any-frequency jitter attenuator/clock multiplier with integrated crystal reference, delivering 71 fs RMS phase jitter (Grade E), ultra-low-jitter clock synthesis from 100 Hz to 1028 MHz differential outputs, and enhanced hitless switching for telecom and high-speed SerDes applications.

For engineers reviewing the SI5394J-A-GMR datasheet, SI5394J-A-GMR pinout, SI5394J-A-GMR application, or SI5394J-A-GMR equivalent, this device serves as a programmable, NVM-configurable timing solution for SyncE-compliant line cards, 56G PAM4 SerDes clocking, and OTN transponder systems requiring stable holdover and sub-0.2 ns phase transients during input switching.

Technical Context

The SI5394J-A-GMR implements a fourth-generation DSPLL architecture with integrated crystal oscillator (Grade J), enabling free-run, locked, and holdover modes without external XTAL components. Its MultiSynth™ dividers support independent integer/fractional synthesis per output, with programmable DSPLL loop bandwidth (0.1 Hz–4 kHz) and dynamic phase adjustment.

It features four differential/LVCMOS inputs (8 kHz–750 MHz), four configurable LVDS/LVPECL/LVCMOS/HCSL/CML outputs (100 Hz–1028 MHz), status monitoring (LOS/OOF/LOL), and I²C/SPI interface with in-circuit programmable OTP memory - all operating across –40°C to +85°C with 1.8 V core and 3.3 V analog supply rails.

Key Specifications

Pinout & Package

SI5394J-A-GMR uses a 44-pin LGA package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5394 Family Reference Manual Rev. 1.3 (Section 6.1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5394K-A-GMR, SI5394J-A-GMR provides broader frequency coverage critical for 100G+ SerDes; versus SI5344D-A-GMR, it eliminates XTAL placement and improves holdover stability via integrated resonator and 120 s averaging - directly reducing design risk in carrier-grade SyncE systems.

Availability

SI5394J-A-GMR is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line cards requiring stable component supply, long-term lifecycle assurance, and RoHS-6 compliance.

Supply support for SI5394J-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The SI5394J-A-GMR belongs to Skyworks' Si539x family of ultra-low-jitter jitter attenuators, designed specifically for next-generation telecom infrastructure, optical transport, and high-speed data center interconnects demanding G.8262/G.8262.1 compliance.

FAQ

What is the phase jitter performance of the SI5394J-A-GMR?

The SI5394J-A-GMR delivers 71 fs RMS phase jitter (12 kHz–20 MHz offset) in Grade E configuration. This value is measured under specified conditions including 156.25 MHz output, LVDS format, and 1.8 V/3.3 V supplies. The jitter performance enables direct compliance with IEEE 802.3bj and OIF CEI-56G requirements for 56G PAM4 SerDes clocking. SI5394J-A-GMR achieves this using fourth-generation DSPLL filtering and integrated crystal reference stability.

Does the SI5394J-A-GMR require an external crystal?

No, the SI5394J-A-GMR does not require an external crystal because it belongs to the J-grade family with an integrated MEMS-based crystal resonator. This eliminates external XTAL components, load capacitors, and associated PCB layout constraints. Connecting an external clock to XA/XB pins on SI5394J-A-GMR is prohibited and may damage the device. SI5394J-A-GMR relies solely on its internal reference for free-run and holdover operation.

How many outputs does the SI5394J-A-GMR support, and what formats are available?

The SI5394J-A-GMR supports four fully independent differential clock outputs (OUT0–OUT3). Each output is programmable for LVDS, LVPECL, LVCMOS, CML, or HCSL signaling with adjustable amplitude and common-mode voltage. Output frequencies range from 100 Hz to 1028 MHz differential (or 100 Hz to 250 MHz LVCMOS), and each can be configured with distinct integer/fractional synthesis parameters via ClockBuilder Pro or register writes.

What is the purpose of the holdover mode in the SI5394J-A-GMR?

Holdover mode in the SI5394J-A-GMR maintains stable clock output when all input references fail. It calculates a final holdover frequency from up to 120 seconds of stored historical frequency data, using a programmable averaging window to minimize phase disturbance. The SI5394J-A-GMR's integrated crystal ensures holdover accuracy within ±50 ppm over temperature, satisfying ITU-T G.8262 wander requirements for telecom applications where input redundancy is critical.

Can the SI5394J-A-GMR perform hitless switching between input clocks?

Yes, the SI5394J-A-GMR supports enhanced hitless switching with typical phase transients of 0.2 ns when switching between input clocks that are frequency-locked (e.g., integer-related or identical frequencies). This feature is implemented in hardware via DSPLL phase absorption and requires no software intervention. It is validated for 8 kHz, 19.44 MHz, and 25 MHz inputs, preserving signal integrity in SyncE and OTN systems during automatic clock source failover.