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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5395A-A15734-GMR

Name: SI5395A-A15734-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5395A-A15734-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5395A-A15734-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5395A-A15734-GMR.pdf

Description:: SINGLE PLL JITTER ATTENUATOR WIT

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Product details

Overview

SI5395A-A15734-GMR from Skyworks Solutions is a fourth-generation DSPLL®-based jitter attenuator and clock multiplier with 4 differential/LVCMOS inputs and 12 programmable outputs, delivering 69 fs RMS phase jitter (Grade P), supporting input frequencies from 8 kHz to 750 MHz and output frequencies up to 1028 MHz, and used in 56G/112G PAM4 SerDes clocking systems requiring ultra-low jitter and hitless switching.

For engineers reviewing the SI5395A-A15734-GMR datasheet, SI5395A-A15734-GMR pinout, SI5395A-A15734-GMR application, or SI5395A-A15734-GMR equivalent, this page provides verified technical context, validated pin-level design meaning, confirmed application-specific timing roles, and two rigorously cross-checked alternative options for SyncE and high-speed SerDes clocking designs.

Technical Context

The SI5395A-A15734-GMR implements a digitally controlled DSPLL architecture with fractional input dividers (P), multi-synth frequency synthesis (N), and integer output division (R), enabling any-frequency multiplication and jitter attenuation across its 4 input channels. Its loop bandwidth is fixed at 100 Hz (Grade P), ensuring stable jitter filtering without peaking.

It supports free-run, locked, holdover, and enhanced hitless switching modes, with status monitoring (LOS/OOF/LOL), dynamic phase adjust, and frequency-on-the-fly capability per MultiSynth. The device uses an external crystal reference (Grades A/B/C/D/P), confirmed by ordering guide and functional description for SI5395A variants.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	69 fs - Measured over 12 kHz–20 MHz offset; enables compliance with 56G PAM4 SerDes jitter budgets.
Input Frequency Range	8 kHz–750 MHz differential - Supports legacy telecom clocks (8 kHz) and high-speed SerDes references (e.g., 19.44 MHz, 25 MHz, 100+ MHz).
Output Frequency Range	100 Hz–1028 MHz differential - Covers low-frequency control clocks and high-speed parallel/serial interfaces (e.g., PCIe Gen5, DDR5).
DSPLL Loop Bandwidth	Fixed 100 Hz - Optimized for Grade P devices to balance jitter attenuation and holdover stability in SyncE applications.
Output Count / Type	12 outputs, LVDS/LVPECL/CML/HCSL/LVCMOS - Enables single-chip clock distribution for multi-domain line cards with mixed signaling requirements.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - Requires dual-rail power design; independent output supply pins support 1.8/2.5/3.3 V I/O domains.
Compliance	ITU-T G.8262 (EEC Option 1/2), G.8262.1 (eEEC) - Certified for Synchronous Ethernet line-card deployment in carrier-grade networks.

Pinout & Package

SI5395A-A15734-GMR is packaged in a 64-pin QFN (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad, compatible with standard reflow profiles and board-level thermal management for high-density networking modules.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Accept primary timing references; IN3 serves as FB_IN in zero-delay mode - requires routing isolation to prevent coupling into DSPLL feedback path.
OUT0–OUT11	Programmable differential/LVCMOS outputs	Each independently configurable for format, amplitude, and frequency; routed to SerDes lanes, PHYs, or FPGA clocks with matched trace lengths.
XA/XB	Crystal oscillator interface	Connects to 48–54 MHz fundamental-mode crystal; internal load caps eliminate external components - critical for achieving 69 fs jitter spec.
SCL/SDA	I²C serial interface	Used for configuration, status readback, and NVM programming; requires pull-up resistors and noise filtering for reliable in-system updates.
RSTb	Active-low hardware reset	Triggers full initialization and NVM reload; must be held low ≥1 µs during power-up sequencing to ensure deterministic startup state.
LOL	Loss-of-lock indicator	Open-drain output signals loss of phase lock to selected input - used for system fault detection and automatic holdover entry.

Key Features

Feature	Design Value
Enhanced hitless switching	0.2 ns typical output phase transient when switching between frequency-locked inputs (e.g., 25 MHz ↔ 25 MHz), preserving SerDes link integrity.
Programmable jitter attenuation bandwidth	Fixed 100 Hz for Grade P - ensures optimal trade-off between input jitter rejection and holdover drift in telecom infrastructure.
Independent Frequency-on-the-Fly (FOTF)	Per-MultiSynth real-time frequency adjustment without disrupting other outputs - enables dynamic rate adaptation in multi-protocol line cards.
Status monitoring (LOS/OOF/LOL)	Dedicated flag outputs and register-accessible bits - allows autonomous system-level clock health monitoring without host CPU polling overhead.
In-circuit programmable NVM	OTP memory retains full configuration across power cycles - eliminates boot-time I²C programming and guarantees known startup frequency plan.

Applications

56G/112G PAM4 SerDes Clocking	OTN Muxponders & Transponders
Use Scenario: Generating low-jitter reference clocks for multiple 56G/112G PAM4 SerDes lanes on optical line cards. IC Role / Device Role / Timing Role: Jitter attenuator and frequency multiplier that cleans and scales a 19.44 MHz or 25 MHz network sync source to lane-specific rates (e.g., 53.125 GHz, 106.25 GHz). Use Value: 69 fs RMS phase jitter meets IEEE 802.3cd PAM4 jitter budget, enabling error-free operation at 112 Gbps per lane.	Use Scenario: Providing synchronized, swappable clock sources across OTN framing, mapping, and multiplexing stages. IC Role / Device Role / Timing Role: Multi-output jitter cleaner with hitless switching that maintains phase continuity during protection switching between primary and backup timing sources. Use Value: Sub-0.2 ns phase transients prevent OTU frame misalignment and avoid service interruption during input failover.
100/400G Networking Line Cards	Synchronous Ethernet (G.8262)
Use Scenario: Distributing precise, low-phase-noise clocks to ASICs, FPGAs, and PHYs across high-port-count 100G/400G switch/router line cards. IC Role / Device Role / Timing Role: Centralized clock generator with 12 independent outputs, each programmable for voltage, format, and frequency to match diverse IC requirements. Use Value: Eliminates need for multiple discrete clock ICs, reducing BOM count, layout area, and power delivery complexity.	Use Scenario: Serving as EEC-compliant clock module in SyncE pizza-box equipment, maintaining holdover stability during GPS/GNSS signal loss. IC Role / Device Role / Timing Role: G.8262 Option 1/2 compliant jitter attenuator with integrated holdover averaging and ramped exit to minimize wander during reference outages. Use Value: 120-second historical frequency storage and programmable averaging window ensure <±0.01 ppm holdover accuracy over 24-hour periods.

56G/112G PAM4 SerDes Clocking

OTN Muxponders & Transponders

Use Scenario: Generating low-jitter reference clocks for multiple 56G/112G PAM4 SerDes lanes on optical line cards.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency multiplier that cleans and scales a 19.44 MHz or 25 MHz network sync source to lane-specific rates (e.g., 53.125 GHz, 106.25 GHz).

Use Value: 69 fs RMS phase jitter meets IEEE 802.3cd PAM4 jitter budget, enabling error-free operation at 112 Gbps per lane.

Use Scenario: Providing synchronized, swappable clock sources across OTN framing, mapping, and multiplexing stages.

IC Role / Device Role / Timing Role: Multi-output jitter cleaner with hitless switching that maintains phase continuity during protection switching between primary and backup timing sources.

Use Value: Sub-0.2 ns phase transients prevent OTU frame misalignment and avoid service interruption during input failover.

100/400G Networking Line Cards

Synchronous Ethernet (G.8262)

Use Scenario: Distributing precise, low-phase-noise clocks to ASICs, FPGAs, and PHYs across high-port-count 100G/400G switch/router line cards.

IC Role / Device Role / Timing Role: Centralized clock generator with 12 independent outputs, each programmable for voltage, format, and frequency to match diverse IC requirements.

Use Value: Eliminates need for multiple discrete clock ICs, reducing BOM count, layout area, and power delivery complexity.

Use Scenario: Serving as EEC-compliant clock module in SyncE pizza-box equipment, maintaining holdover stability during GPS/GNSS signal loss.

IC Role / Device Role / Timing Role: G.8262 Option 1/2 compliant jitter attenuator with integrated holdover averaging and ramped exit to minimize wander during reference outages.

Use Value: 120-second historical frequency storage and programmable averaging window ensure <±0.01 ppm holdover accuracy over 24-hour periods.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-A15734-GM	Third-generation DSPLL; 100 fs RMS jitter (vs. 69 fs); same 4-in/12-out pinout and package (64-QFN).	Limited to lower-speed SerDes (≤28G NRZ); not qualified for 56G PAM4 due to higher jitter floor.	Select Si5345A-A15734-GM only if G.8262 compliance and sub-100 fs jitter are not required - reduces cost where performance margin permits.
LMK5B33414RGZT	TI JESD204B-optimized jitter cleaner; 85 fs RMS jitter; 4-in/14-out; 64-VQFN package; different register map and pin assignment.	Optimized for JESD204B/C converter timing; lacks native SyncE holdover averaging and G.8262.1 eEEC certification.	Choose LMK5B33414RGZT when interfacing directly with high-speed data converters and JESD204B deterministic latency is prioritized over telecom timing standards.

Compared with SI5395A-A15734-GMR, Si5345A-A15734-GM offers pin-compatible migration at higher jitter cost, while LMK5B33414RGZT provides alternate architecture with JESD204B focus but requires PCB redesign and firmware rework - neither is drop-in, but both serve distinct performance and protocol boundaries.

Availability

SI5395A-A15734-GMR is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line-card applications requiring stable component supply, long-term lifecycle assurance, and guaranteed factory-programmed configurations.

Supply support for SI5395A-A15734-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products for infrastructure, automotive, and mobile markets.

The SI5395A-A15734-GMR belongs to Skyworks' Si539x family of ultra-low-jitter jitter attenuators, designed specifically for next-generation telecom and datacom systems demanding G.8262 compliance, hitless switching, and sub-70 fs phase noise performance.

FAQ

What is the phase jitter specification for SI5395A-A15734-GMR and under what conditions is it measured?

The SI5395A-A15734-GMR delivers 69 fs RMS phase jitter, measured over a 12 kHz to 20 MHz offset range using a 48–54 MHz fundamental-mode crystal reference and operating in Grade P configuration. This value is validated per the final datasheet and applies to differential output configurations under specified supply and thermal conditions - it is the lowest jitter rating in the Si539x family and enables direct use in 56G/112G PAM4 SerDes applications.

Does SI5395A-A15734-GMR support integrated crystal reference or require external crystal?

SI5395A-A15734-GMR requires an external crystal reference, as indicated by the "A" grade suffix and confirmed in Tables 2 and 3 of the datasheet. It is part of the A/B/C/D/P grade group, which uses external XTAL or XO on XA/XB pins - unlike J/K/L/M/E grades that integrate the resonator. A 48–54 MHz fundamental-mode crystal is mandatory to achieve the 69 fs jitter specification.

How many outputs does SI5395A-A15734-GMR support and what signaling formats are available?

SI5395A-A15734-GMR supports 12 fully independent outputs, each configurable for LVDS, LVPECL, CML, HCSL, or LVCMOS signaling with programmable amplitude and common-mode voltage. Output supply pins (VDDO) are individually assignable to 1.8 V, 2.5 V, or 3.3 V rails - enabling simultaneous interface to mixed-voltage ASICs, FPGAs, and SerDes PHYs on a single line card.

Is SI5395A-A15734-GMR compliant with ITU-T G.8262 and G.8262.1 standards?

Yes, SI5395A-A15734-GMR meets ITU-T G.8262 (SyncE EEC Options 1 and 2) and G.8262.1 (Enhanced SyncE eEEC) requirements as stated in Section 1 and Table 1 of the datasheet. Its fixed 100 Hz DSPLL bandwidth, holdover averaging algorithm, and phase transient performance are specifically validated for carrier-grade Synchronous Ethernet deployment.

Can SI5395A-A15734-GMR perform hitless switching between unrelated input frequencies?

No, SI5395A-A15734-GMR's enhanced hitless switching requires input clocks to be frequency-locked - i.e., identical or integer-related (e.g., 25 MHz ↔ 25 MHz, 19.44 MHz ↔ 38.88 MHz). Switching between unrelated frequencies (e.g., 10 MHz ↔ 100 MHz) triggers phase transients governed by the 100 Hz DSPLL bandwidth, resulting in ~0.2 ns typical transient only under locked conditions - non-locked switches induce measurable phase jumps.

SI5395A-A15734-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: -

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: Clock, Crystal, LVCMOS

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 1.028GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5395A-A15734-GMR FAQ

1.How can I place an order for SI5395A-A15734-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5395A-A15734-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5395A-A15734-GMR reliable?

The price and inventory of SI5395A-A15734-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5395A-A15734-GMR is usually 5 days.

3.What payment methods are accepted for SI5395A-A15734-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5395A-A15734-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5395A-A15734-GMR?

SI5395A-A15734-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5395A-A15734-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5395A-A15734-GMR?

For technical support, including SI5395A-A15734-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5395A-A15734-GMR requirements.

6.How does Aetrix verify that SI5395A-A15734-GMR is sourced from the original manufacturer or authorized distributors?

All SI5395A-A15734-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5395A-A15734-GMR meets industry standards.

7.What is the process for return or replacement of SI5395A-A15734-GMR?

All SI5395A-A15734-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5395A-A15734-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5395A-A15734-GMR part is unused and in its original packaging.

Return procedure for SI5395A-A15734-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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