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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5395A-A-GMR

Name: SI5395A-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5395A-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5395A-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5395A-A-GMR.pdf

Description:: IC JITTER ATTENUATOR

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Product details

Overview

SI5395A-A-GMR from Skyworks Solutions is a fourth-generation DSPLL®-based jitter attenuator and clock multiplier IC with ultra-low 69 fs RMS phase jitter (P-grade), 4 differential/LVCMOS inputs, 12 programmable outputs, and integrated non-volatile memory. It operates in free-run, locked, or holdover modes and supports hitless switching between input clocks for 56G PAM4 SerDes clocking in telecom line cards.

For engineers reviewing the SI5395A-A-GMR datasheet, SI5395A-A-GMR pinout, SI5395A-A-GMR application, or SI5395A-A-GMR equivalent, key selection criteria include its 69 fs jitter performance, 100 Hz–1028 MHz differential output range, 0.1 Hz–4 kHz configurable DSPLL loop bandwidth, external crystal reference architecture, and compatibility with ClockBuilder Pro configuration software.

Technical Context

The SI5395A-A-GMR implements a digitally controlled oscillator (DCO)-capable DSPLL with fractional-N synthesis, enabling any-frequency multiplication from any input frequency. Its architecture integrates four independent MultiSynth™ dividers per output path, supporting integer and fractional synthesis modes with independent frequency-on-the-fly control.

It features programmable holdover with 120-second frequency history averaging, enhanced hitless switching (0.2 ns typical phase transient), and dual-loop operation: a high-bandwidth Fastlock mode (100 Hz–4 kHz) for rapid lock acquisition and a stable main DSPLL loop (0.1 Hz–4 kHz) for jitter attenuation-except in Grade P devices where loop bandwidth is fixed at 100 Hz.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	69 fs - Measured over 12 kHz–20 MHz offset; enables compliance with 56G/112G PAM4 SerDes jitter budgets.
Input Frequency Range	8 kHz–750 MHz (differential); supports legacy telecom timing signals and high-speed reference clocks.
Output Frequency Range	100 Hz–1028 MHz (differential); covers SyncE, OTN, and Ethernet PHY clocking requirements.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz (configurable); determines jitter attenuation profile and holdover stability trade-off.
Output Count / Type	12 LVDS/LVPECL/CML/HCSL/LVCMOS outputs; each independently format- and amplitude-programmable.
Reference Architecture	External crystal (48–54 MHz XTAL) - eliminates need for external load capacitors and reduces board-level noise coupling.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins support 1.8/2.5/3.3 V I/O domains.

Pinout & Package

SI5395A-A-GMR is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5395 Family Reference Manual (Rev. 1.3, Section 5.1) and validated against official pinout diagrams in UG335.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Accept primary timing references; IN3 serves as FB_IN in zero-delay mode.
OUT0–OUT11	Programmable clock outputs	Support LVDS/LVPECL/CML/HCSL/LVCMOS; each with independent format, amplitude, and delay control.
XA/XB	Crystal oscillator interface	Connects to 48–54 MHz fundamental-mode crystal; internal load caps eliminate external components.
SCL/SDA	I²C serial interface	Two-wire bus for configuration, status readback, and NVM programming; supports hot-plug operation.
RSTb	Active-low hardware reset	Triggers full initialization and NVM reload; required before first-time configuration or after power-up.
LOL	Loss-of-Lock indicator	Open-drain output asserts low when DSPLL loses phase lock to selected input clock.

Key Features

Feature	Design Value
Ultra-low jitter synthesis	69 fs RMS (P-grade) enables direct use in 56G PAM4 SerDes CDR clocking without additional cleanup.
Hitless input switching	0.2 ns typical phase transient allows seamless failover between synchronized telecom references (e.g., 8 kHz, 19.44 MHz).
Programmable holdover	120-second frequency history buffer with user-defined averaging window ensures stable output during input loss.
In-circuit NVM programming	Non-volatile OTP memory retains factory or field-programmed configuration; powers up ready-to-operate.
MultiSynth independence	Each of 12 outputs supports independent frequency-on-the-fly updates without disrupting other outputs.

Applications

56G/112G PAM4 SerDes Clocking	OTN Muxponders & Transponders
Use Scenario: Generating low-jitter reference clocks for 56G/112G PAM4 SerDes lanes in optical transport modules. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier providing clean, frequency-agile outputs synchronized to network timing sources. Use Value: 69 fs RMS jitter meets IEEE 802.3cd and OIF CEI-112G-LR jitter masks without external cleanup circuits.	Use Scenario: Clock synthesis and synchronization in OTN line cards handling multiple client interfaces (e.g., 100G, 400G). IC Role / Device Role / Timing Role: Multi-domain clock generator delivering ITU-T G.8262-compliant SyncE and G.709 OTU frame timing. Use Value: Supports up to 3 independent frequency domains (Grade P), enabling simultaneous OTU4, OTU3, and client-layer timing.
100G/400G Synchronous Ethernet	Medical Imaging Systems
Use Scenario: Providing EEC Option 1/2 compliant clocks for 100G/400GbE line cards in metro/core routers. IC Role / Device Role / Timing Role: Primary timing IC meeting ITU-T G.8262 and G.8262.1 eEEC standards for SyncE distribution. Use Value: Integrated holdover and hitless switching maintain sub-50 ppb wander during reference loss, satisfying G.8262.1 Class C requirements.	Use Scenario: Low-phase-noise clock generation for ultrasound beamforming ASICs and MRI gradient controllers. IC Role / Device Role / Timing Role: Precision jitter cleaner converting noisy system clocks into stable sampling clocks for ADCs/DACs. Use Value: 69 fs jitter directly improves SNR in time-domain signal processing, reducing image artifacts in real-time B-mode imaging.

56G/112G PAM4 SerDes Clocking

OTN Muxponders & Transponders

Use Scenario: Generating low-jitter reference clocks for 56G/112G PAM4 SerDes lanes in optical transport modules.

IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier providing clean, frequency-agile outputs synchronized to network timing sources.

Use Value: 69 fs RMS jitter meets IEEE 802.3cd and OIF CEI-112G-LR jitter masks without external cleanup circuits.

Use Scenario: Clock synthesis and synchronization in OTN line cards handling multiple client interfaces (e.g., 100G, 400G).

IC Role / Device Role / Timing Role: Multi-domain clock generator delivering ITU-T G.8262-compliant SyncE and G.709 OTU frame timing.

Use Value: Supports up to 3 independent frequency domains (Grade P), enabling simultaneous OTU4, OTU3, and client-layer timing.

100G/400G Synchronous Ethernet

Medical Imaging Systems

Use Scenario: Providing EEC Option 1/2 compliant clocks for 100G/400GbE line cards in metro/core routers.

IC Role / Device Role / Timing Role: Primary timing IC meeting ITU-T G.8262 and G.8262.1 eEEC standards for SyncE distribution.

Use Value: Integrated holdover and hitless switching maintain sub-50 ppb wander during reference loss, satisfying G.8262.1 Class C requirements.

Use Scenario: Low-phase-noise clock generation for ultrasound beamforming ASICs and MRI gradient controllers.

IC Role / Device Role / Timing Role: Precision jitter cleaner converting noisy system clocks into stable sampling clocks for ADCs/DACs.

Use Value: 69 fs jitter directly improves SNR in time-domain signal processing, reducing image artifacts in real-time B-mode imaging.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5395P-A-GMR	Same 64-QFN package and pinout; fixed 100 Hz DSPLL loop bandwidth; supports up to 3 frequency domains.	Optimized for highest-jitter-performance 56G SerDes; lacks configurable loop bandwidth but guarantees 69 fs spec.	Select when absolute jitter floor is critical and loop bandwidth flexibility is unnecessary.
Si5345A-A-GMR	Drop-in compatible predecessor; 75 fs RMS jitter; same 64-QFN footprint; no integrated holdover history buffer.	Legacy design-in replacement; suitable for less demanding 25G/100G applications where 69 fs is not required.	Choose for cost-sensitive upgrades where existing Si5345 layout and firmware can be reused.

Compared with SI5395A-A-GMR, Si5395P-A-GMR delivers guaranteed 69 fs jitter at fixed 100 Hz loop bandwidth but sacrifices configurability, while Si5345A-A-GMR offers proven drop-in compatibility with higher jitter and no programmable holdover-making SI5395A-A-GMR optimal for new designs requiring both flexibility and ultra-low jitter.

Availability

SI5395A-A-GMR is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line cards requiring stable component supply across multi-year production cycles.

Supply support for SI5395A-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5395 family is engineered as a high-performance jitter attenuator and clock multiplier platform targeting next-generation optical transport, 5G fronthaul/backhaul, and precision test equipment requiring sub-100 fs jitter and multi-domain timing agility.

FAQ

What is the phase jitter specification for SI5395A-A-GMR and under what conditions is it measured?

The SI5395A-A-GMR achieves 69 fs RMS phase jitter (integrated from 12 kHz to 20 MHz offset), specified for Grade P devices using a 48 MHz external crystal reference and operating in locked mode. This value is confirmed in the Skyworks Final Data Sheet (206689B, April 2025) and applies to differential outputs configured per recommended layout guidelines. SI5395A-A-GMR maintains this jitter performance across its full 100 Hz–1028 MHz output range when synthesizing integer or fractional frequencies.

Does SI5395A-A-GMR support hitless switching between input clocks, and what are the requirements?

Yes, SI5395A-A-GMR supports enhanced hitless switching with ≤0.2 ns typical phase transient. It requires that the two input clocks be frequency-locked-either identical or related by an exact integer ratio-and that the DSPLL is configured for hitless mode via register control. The feature is validated for 8 kHz, 19.44 MHz, and 25 MHz inputs per Skyworks AN1151, and SI5395A-A-GMR absorbs phase differences internally without propagating glitches to outputs.

What package type and footprint does SI5395A-A-GMR use, and is it compatible with automated assembly?

SI5395A-A-GMR uses a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad, fully compliant with IPC-7351B standards. Its lead-free, RoHS-6-compliant construction and standard reflow profile (per JEDEC J-STD-020) ensure compatibility with high-volume SMT assembly lines. The SI5395A-A-GMR footprint matches Skyworks' recommended land pattern in UG335 and supports standard SPI/I²C routing without impedance discontinuities.

Can SI5395A-A-GMR operate without an external crystal, and what are the reference options?

No-SI5395A-A-GMR (Grade A) requires an external 48–54 MHz fundamental-mode crystal connected to XA/XB pins; it does not include an integrated resonator. The device uses internal load capacitors (no external caps needed) and supports optional external XO input via REFCLK mode. SI5395A-A-GMR cannot use integrated reference variants (e.g., Si5395J), and connecting external clock sources to integrated-reference grades risks damage per Skyworks datasheet warning.

How is SI5395A-A-GMR configured, and is factory programming available?

SI5395A-A-GMR is configured via I²C or SPI interface using Skyworks ClockBuilder Pro software, which generates register maps and validates frequency plans. It includes on-chip OTP NVM to retain configuration across power cycles. Factory preprogrammed units are available with custom part numbers (e.g., Si5395A-Axxxxx-GM), where "xxxxx" encodes the specific frequency plan, output formats, and operational modes programmed prior to shipment.

SI5395A-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5395A-A-GMR FAQ

1.How can I place an order for SI5395A-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5395A-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5395A-A-GMR reliable?

The price and inventory of SI5395A-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5395A-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5395A-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5395A-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5395A-A-GMR?

SI5395A-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5395A-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5395A-A-GMR?

For technical support, including SI5395A-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5395A-A-GMR requirements.

6.How does Aetrix verify that SI5395A-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5395A-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5395A-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5395A-A-GMR?

All SI5395A-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5395A-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5395A-A-GMR part is unused and in its original packaging.

Return procedure for SI5395A-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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