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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5395B-A15654-GM

Name: SI5395B-A15654-GM
Brand: Skyworks Solutions Inc.
SKU: SI5395B-A15654-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5395B-A15654-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5395B-A15654-GM.pdf

Description:: SINGLE PLL JITTER ATTENUATOR WIT

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5395B-A15654-GM from Skyworks Solutions is a fourth-generation DSPLL-based jitter attenuator and clock multiplier IC with 4 differential/LVCMOS inputs and 12 programmable outputs, delivering 71 fs RMS phase jitter (Grade E), 0.0001–350 MHz output frequency range, and integrated reference oscillator for board-space-constrained SyncE and 56G SerDes applications.

For engineers reviewing the SI5395B-A15654-GM datasheet, SI5395B-A15654-GM pinout, SI5395B-A15654-GM application, or SI5395B-A15654-GM equivalent, this device supports hitless switching between gapped or integer-related clocks, programmable DSPLL loop bandwidth (0.1 Hz–4 kHz), G.8262/E.8262.1 compliance, and in-circuit NVM configuration via I²C/SPI - critical for telecom line card and medical imaging timing integrity.

Technical Context

The SI5395B-A15654-GM implements a digitally controlled oscillator (DCO)-capable DSPLL architecture with fractional input dividers (P), MultiSynth™ frequency synthesis (N), and configurable R-division to generate any output frequency from any input. Its integrated reference oscillator eliminates external crystal components and acoustic noise sensitivity during thermal ramping.

It operates across free-run, locked, holdover, and enhanced hitless switching modes, with programmable holdover history window (up to 120 s) and ramped frequency transitions (0.2–40,000 ppm/s). The device uses independent output supply pins (1.8/2.5/3.3 V) and supports LVDS, LVPECL, LVCMOS, CML, and HCSL output formats with amplitude control.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	71 fs - meets stringent 56G PAM4 SerDes sampling margin requirements
Output Frequency Range	0.0001–350 MHz - supports low-frequency control clocks and high-speed data links
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - accommodates sync sources from 8 kHz TDM to 750 MHz reference clocks
DSPLL Loop Bandwidth	0.1 Hz–4 kHz - enables precise jitter attenuation tuning for SyncE wander suppression or fast lock acquisition
Output Count / Type	12 differential or LVCMOS outputs - provides full clock tree coverage for multi-domain SoCs and FPGA-based systems
Reference Source	Integrated oscillator - removes need for external crystal, reduces BOM count, and improves reliability in space-constrained designs
Compliance	ITU-T G.8262 (EEC Options 1 & 2), G.8262.1 (eEEC) - certified for Synchronous Ethernet transport infrastructure

Pinout & Package

SI5395B-A15654-GM is housed in a 64-pin LGA package (9 × 9 mm, 0.5 mm pitch), optimized for thermal performance and high-density PCB layouts in telecom and test equipment.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS input clock terminals	Support automatic/manual selection of up to four redundant timing sources with LOS/OOF monitoring
OUT0–OUT11	Programmable output clock drivers	Configurable for LVDS/LVPECL/LVCMOS/CML/HCSL with independent voltage supplies and amplitude control
XA/XB	Crystal oscillator interface	Internally terminated; not used in Grade J/K/L/M/E devices - SI5395B-A15654-GM uses integrated reference only
SCL/SDA or SCLK/SDIO/CS	I²C or SPI serial interface	Enables in-system programming of NVM and real-time frequency-on-the-fly updates without reset
RSTb	Hardware reset input	Triggers full initialization and NVM reload - required before stable clock output after power-up
LOL/LOS/OOF	Status flag outputs	Provide real-time lock loss, loss of signal, and out-of-frequency alerts for system-level fault management

Key Features

Feature	Design Value
Enhanced hitless switching	0.2 ns typical output phase transient during input clock switchover - preserves SerDes eye opening during redundancy handover
Programmable holdover history window	Configurable 1–120 s averaging window - minimizes frequency step error when primary reference fails in telecom base stations
Frequency-on-the-fly (FOTF)	Independent MultiSynth reconfiguration without disrupting other outputs - enables dynamic rate adaptation in packet-optical systems
Digital Controlled Oscillator (DCO) mode	0.001 ppb step size with FINC/FDEC pin control - supports fine-grained frequency calibration in test and measurement instruments
Zero-delay mode	IN3 repurposed as FB_IN - allows precise phase alignment for feedback-based clock distribution networks

Applications

56G/112G PAM4 SerDes Clocking	OTN Muxponders & Transponders
Use Scenario: High-speed optical interconnects requiring sub-100-fs jitter clocks for 56G/112G PAM4 signaling in AI accelerators and switch ASICs. IC Role / Device Role / Timing Role: Jitter attenuator and frequency multiplier generating clean, phase-aligned clocks from noisy or variable-rate references. Use Value: 71 fs RMS jitter ensures >25 dB SNR margin at 56G, enabling reliable forward error correction and extended reach without retiming.	Use Scenario: Optical transport network equipment needing multiple synchronized clocks for OTU4 framing, FEC processing, and client-side interfaces. IC Role / Device Role / Timing Role: Multi-output clock generator with G.8262 compliance and holdover stability for uninterrupted operation during reference loss. Use Value: Integrated reference and 120-second holdover history enable <100 ppb frequency drift over 24 hours - meeting ITU-T G.8262 eEEC requirements.
100/400G Networking Line Cards	Medical Imaging Systems
Use Scenario: Carrier-grade routers and switches requiring deterministic latency, low-jitter clocks for MAC, PHY, and packet buffer timing across multiple lanes. IC Role / Device Role / Timing Role: Centralized timing hub distributing 12 independently configured clocks with hitless failover between primary and backup references. Use Value: 0.2 ns phase transient during hitless switching prevents packet loss during reference switchover in 400G coherent line cards.	Use Scenario: MRI and PET scanners demanding ultra-low-jitter sampling clocks for analog-to-digital conversion of RF signals with >16-bit ENOB. IC Role / Device Role / Timing Role: Low-phase-noise clock source replacing discrete crystal oscillators and PLLs to reduce EMI and layout complexity. Use Value: 71 fs RMS jitter translates to <0.001° phase error at 100 MHz - preserving image resolution and contrast fidelity in time-of-flight reconstruction.

56G/112G PAM4 SerDes Clocking

OTN Muxponders & Transponders

Use Scenario: High-speed optical interconnects requiring sub-100-fs jitter clocks for 56G/112G PAM4 signaling in AI accelerators and switch ASICs.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency multiplier generating clean, phase-aligned clocks from noisy or variable-rate references.

Use Value: 71 fs RMS jitter ensures >25 dB SNR margin at 56G, enabling reliable forward error correction and extended reach without retiming.

Use Scenario: Optical transport network equipment needing multiple synchronized clocks for OTU4 framing, FEC processing, and client-side interfaces.

IC Role / Device Role / Timing Role: Multi-output clock generator with G.8262 compliance and holdover stability for uninterrupted operation during reference loss.

Use Value: Integrated reference and 120-second holdover history enable <100 ppb frequency drift over 24 hours - meeting ITU-T G.8262 eEEC requirements.

100/400G Networking Line Cards

Medical Imaging Systems

Use Scenario: Carrier-grade routers and switches requiring deterministic latency, low-jitter clocks for MAC, PHY, and packet buffer timing across multiple lanes.

IC Role / Device Role / Timing Role: Centralized timing hub distributing 12 independently configured clocks with hitless failover between primary and backup references.

Use Value: 0.2 ns phase transient during hitless switching prevents packet loss during reference switchover in 400G coherent line cards.

Use Scenario: MRI and PET scanners demanding ultra-low-jitter sampling clocks for analog-to-digital conversion of RF signals with >16-bit ENOB.

IC Role / Device Role / Timing Role: Low-phase-noise clock source replacing discrete crystal oscillators and PLLs to reduce EMI and layout complexity.

Use Value: 71 fs RMS jitter translates to <0.001° phase error at 100 MHz - preserving image resolution and contrast fidelity in time-of-flight reconstruction.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5395A-A-GM	External crystal reference (48–54 MHz XTAL); 64-QFN package; supports full 0.0001–1028 MHz output range	Preferred where board layout allows crystal placement and higher-frequency outputs (>350 MHz) are needed	Select Si5395A-A-GM if external crystal is acceptable and wider output bandwidth is required; SI5395B-A15654-GM saves space and improves reliability with integrated reference.
Si5395J-A-GM	Same integrated reference architecture; identical 64-LGA package; supports full 0.0001–1028 MHz output range	Used where full-bandwidth synthesis (not limited to ≤350 MHz) is required in space-constrained SyncE systems	Choose Si5395J-A-GM for full-bandwidth capability with same footprint; SI5395B-A15654-GM trades bandwidth for optimized jitter performance in 350 MHz-limited applications.

Compared with SI5395B-A15654-GM, Si5395A-A-GM requires external crystal layout and offers broader frequency range but higher board area; Si5395J-A-GM matches the LGA package and integrated reference but supports full 1028 MHz output - making SI5395B-A15654-GM the optimal choice for cost-sensitive, space-constrained 350 MHz SyncE deployments.

Availability

SI5395B-A15654-GM is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line cards requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for SI5395B-A15654-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5395 family is designed for ultra-low-jitter clock generation and jitter attenuation in high-speed networking, optical transport, and precision instrumentation - targeting applications where phase noise directly impacts system bit error rate and signal integrity.

FAQ

What is the phase jitter specification of the SI5395B-A15654-GM?

The SI5395B-A15654-GM delivers 71 fs RMS phase jitter (measured over 12 kHz–20 MHz offset), corresponding to Grade E performance per the Skyworks Si5395 datasheet. This value is validated under specified conditions including integrated reference operation, 12 kHz–20 MHz integration bandwidth, and typical load conditions. The SI5395B-A15654-GM achieves this jitter level without requiring external crystal components, making it suitable for high-reliability 56G SerDes clocking.

Does the SI5395B-A15654-GM require an external crystal?

No, the SI5395B-A15654-GM does not require an external crystal. It belongs to the J/K/L/M/E grade family and incorporates an integrated reference oscillator, eliminating the need for external XTAL or XO components. This reduces bill-of-materials count, improves thermal stability, and avoids acoustic noise coupling issues associated with crystal vibration during temperature ramps - a key advantage confirmed in Skyworks' official ordering guide and functional description.

What package type and dimensions does the SI5395B-A15654-GM use?

The SI5395B-A15654-GM uses a 64-pin LGA (Land Grid Array) package measuring 9 × 9 mm with 0.5 mm pitch. This package is specified in Skyworks' Si5395 J/K/L/M/E ordering guide and is distinct from the QFN variant used by A/B/C/D/P grades. The LGA construction provides superior thermal dissipation and mechanical robustness for high-density telecom and medical imaging PCB assemblies.

Can the SI5395B-A15654-GM support hitless switching between input clocks?

Yes, the SI5395B-A15654-GM supports enhanced hitless switching with typical output phase transients of 0.2 ns when switching between input clocks that are frequency-locked (e.g., integer-related or same-frequency sources). This feature is implemented in hardware via the DSPLL's fractional input divider architecture and is explicitly documented in the Si5395 datasheet's Functional Description and Hitless Input Switching sections.

Which communication interface does the SI5395B-A15654-GM support for configuration?

The SI5395B-A15654-GM supports both I²C and SPI serial interfaces for register configuration and NVM programming. Interface selection is determined by strap pin settings at power-up, and both protocols allow full in-circuit programming without requiring device reset. This dual-interface capability is confirmed in the Skyworks Si5395 Family Reference Manual and Final Data Sheet Section 4.1.

SI5395B-A15654-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL™, MultiSynth™

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: -

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: Clock, Crystal, LVCMOS

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5395B-A15654-GM FAQ

1.How can I place an order for SI5395B-A15654-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5395B-A15654-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5395B-A15654-GM reliable?

The price and inventory of SI5395B-A15654-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5395B-A15654-GM is usually 5 days.

3.What payment methods are accepted for SI5395B-A15654-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5395B-A15654-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5395B-A15654-GM?

SI5395B-A15654-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5395B-A15654-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5395B-A15654-GM?

For technical support, including SI5395B-A15654-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5395B-A15654-GM requirements.

6.How does Aetrix verify that SI5395B-A15654-GM is sourced from the original manufacturer or authorized distributors?

All SI5395B-A15654-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5395B-A15654-GM meets industry standards.

7.What is the process for return or replacement of SI5395B-A15654-GM?

All SI5395B-A15654-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5395B-A15654-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5395B-A15654-GM part is unused and in its original packaging.

Return procedure for SI5395B-A15654-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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