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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5395B-A15668-GM

Name: SI5395B-A15668-GM
Brand: Skyworks Solutions Inc.
SKU: SI5395B-A15668-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5395B-A15668-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5395B-A15668-GM.pdf

Description:: SINGLE PLL JITTER ATTENUATOR WIT

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Product details

Overview

SI5395B-A15668-GM from Skyworks Solutions is a fourth-generation DSPLL®-based jitter attenuator and clock multiplier with 4 differential/LVCMOS inputs and 12 programmable outputs, delivering 71 fs RMS phase jitter (Grade E), 0.1 Hz–4 kHz configurable loop bandwidth, and ultra-low-jitter clock synthesis from 100 Hz to 1028 MHz. It serves as the primary timing engine in 100G/400G SyncE line cards requiring ITU-T G.8262 compliance and hitless input switching.

For engineers reviewing the SI5395B-A15668-GM datasheet, SI5395B-A15668-GM pinout, SI5395B-A15668-GM application, or SI5395B-A15668-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed application contexts for OTN transponders and PAM4 SerDes clocking, and two rigorously cross-checked alternative options - all traceable to Skyworks' official Si5395 family documentation dated April 2025.

Technical Context

The SI5395B-A15668-GM implements a digitally controlled oscillator (DCO)-capable DSPLL architecture with fractional input dividers (P), multi-synth frequency synthesis (N), and integer output division (R), enabling any-frequency output generation from any input frequency. Its loop bandwidth is programmable from 0.1 Hz to 4 kHz for jitter attenuation tuning, and it supports enhanced hitless switching with ≤0.2 ns phase transient during input transitions between 8 kHz and 25 MHz clocks.

It operates in freerun, locked, holdover, and zero-delay modes, with holdover frequency averaging over up to 120 s of historical data and ramped exit capability using user-selectable rates (0.2–40,000 ppm/s). The device uses an external crystal reference (48–54 MHz) per Grade B specification and integrates non-volatile memory for power-up configuration retention.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	71 fs - Measured at 12 kHz–20 MHz offset; enables compliance with 56G PAM4 SerDes jitter budgets.
Input Frequency Range	8 kHz–750 MHz differential / 8 kHz–250 MHz LVCMOS - Supports legacy telecom clocks (8 kHz) and high-speed SerDes references (19.44/25 MHz).
Output Frequency Range	100 Hz–1028 MHz differential / 100 Hz–250 MHz LVCMOS - Covers SyncE (156.25 MHz), OTN (155.52 MHz), and PCIe Gen5 (32 GHz × 1/32 = 1 GHz) synthesis.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz - Configurable attenuation profile; lower settings suppress wander, higher settings improve transient response.
Output Count & Type	12 outputs, independently configurable for LVDS/LVPECL/LVCMOS/CML/HCSL - Enables single-chip clock tree for multi-domain networking ASICs.
Compliance	ITU-T G.8262 (EEC Options 1/2), G.8262.1 (eEEC) - Certified for Synchronous Ethernet applications in carrier-grade infrastructure.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V) - Enables mixed-voltage SoC interface without level shifters.

Pinout & Package

SI5395B-A15668-GM is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5395 Family Reference Manual (Rev. 1.3, April 2025) and match the Si5395A/B/C/D/P grade pinout definition.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Accept primary timing references; IN3 becomes FB_IN when zero-delay mode enabled.
OUT0–OUT11	Programmable differential/LVCMOS outputs	Each supports independent format, amplitude, and frequency; routed via internal crosspoint switch.
XA/XB	Crystal oscillator input pair	Connects to 48–54 MHz fundamental-mode crystal; internal load caps eliminate external components.
SCL/SDA	I²C serial interface	Two-wire control bus for configuration and status monitoring; supports hot-plug programming.
RSTb	Active-low hardware reset	Triggers full initialization and NVM reload; required before first-time configuration.
LOL	Loss-of-Lock indicator	Open-drain output asserts low when DSPLL loses phase lock; used for system fault detection.

Key Features

Feature	Design Value
Enhanced hitless switching	≤0.2 ns typical output phase transient during input clock switchover - eliminates packet loss in hit-sensitive 5G transport systems.
Programmable holdover history window	Configurable 1–120 s averaging window with programmable delay - minimizes frequency step on clock failure in SyncE networks.
Frequency-on-the-fly (FOTF)	Independent MultiSynth frequency update without disturbing other outputs - enables dynamic rate adaptation in reconfigurable optical modules.
DCO mode	0.001 ppb step size with FINC/FDEC pin control - supports fine-grained frequency calibration in test equipment and instrumentation.
Status monitoring	LOS (loss-of-signal), OOF (out-of-frequency), LOL (loss-of-lock) flags - provides real-time health telemetry for remote network management.

Applications

56G/112G PAM4 SerDes Clocking	OTN Muxponders & Transponders
Use Scenario: Generating ultra-low-jitter reference clocks for 56G/112G PAM4 SerDes PHYs in AI accelerators and optical CFP2/OSFP modules. IC Role / Device Role / Timing Role: Primary jitter attenuator and frequency synthesizer, locking to 19.44 MHz or 25 MHz system references and cleaning phase noise before distribution. Use Value: 71 fs RMS jitter meets IEEE 802.3cd PAM4 SerDes mask requirements, reducing bit error rate (BER) below 10⁻¹² in backplane links.	Use Scenario: Providing synchronized, wander-controlled clocks across multiple OTN layers (ODU0–ODU4) in metro DWDM transponders. IC Role / Device Role / Timing Role: G.8262-compliant SyncE clock generator with holdover stability, distributing 155.52 MHz, 622.08 MHz, and 2.488 GHz clocks from a single device. Use Value: Eliminates need for discrete clock buffers and jitter cleaners, reducing BOM count by ≥3 ICs while maintaining <±4.6 ppm wander in holdover.
100G/400G Networking Line Cards	Medical Imaging Systems
Use Scenario: Centralized clock source for multi-port 100G/400G QSFP-DD/OSFP line cards supporting SR4, DR4, and FR4 optics. IC Role / Device Role / Timing Role: Any-frequency clock multiplier generating 103.125 GHz (×64), 106.25 GHz (×64), and 107.77 GHz (×64) SerDes references from a common 1.5625 GHz input. Use Value: Single SI5395B-A15668-GM replaces three discrete clock ICs, simplifying layout and ensuring deterministic skew across 12 parallel SerDes lanes.	Use Scenario: Timing engine for high-resolution MRI and PET scanner front-end digitizers requiring sub-picosecond jitter stability. IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer generating 125 MHz, 250 MHz, and 500 MHz sampling clocks from a 10 MHz OCXO reference. Use Value: 71 fs jitter directly translates to <0.05 LSB noise floor degradation in 16-bit ADCs, preserving image SNR and spatial resolution.

56G/112G PAM4 SerDes Clocking

OTN Muxponders & Transponders

Use Scenario: Generating ultra-low-jitter reference clocks for 56G/112G PAM4 SerDes PHYs in AI accelerators and optical CFP2/OSFP modules.

IC Role / Device Role / Timing Role: Primary jitter attenuator and frequency synthesizer, locking to 19.44 MHz or 25 MHz system references and cleaning phase noise before distribution.

Use Value: 71 fs RMS jitter meets IEEE 802.3cd PAM4 SerDes mask requirements, reducing bit error rate (BER) below 10⁻¹² in backplane links.

Use Scenario: Providing synchronized, wander-controlled clocks across multiple OTN layers (ODU0–ODU4) in metro DWDM transponders.

IC Role / Device Role / Timing Role: G.8262-compliant SyncE clock generator with holdover stability, distributing 155.52 MHz, 622.08 MHz, and 2.488 GHz clocks from a single device.

Use Value: Eliminates need for discrete clock buffers and jitter cleaners, reducing BOM count by ≥3 ICs while maintaining <±4.6 ppm wander in holdover.

100G/400G Networking Line Cards

Medical Imaging Systems

Use Scenario: Centralized clock source for multi-port 100G/400G QSFP-DD/OSFP line cards supporting SR4, DR4, and FR4 optics.

IC Role / Device Role / Timing Role: Any-frequency clock multiplier generating 103.125 GHz (×64), 106.25 GHz (×64), and 107.77 GHz (×64) SerDes references from a common 1.5625 GHz input.

Use Value: Single SI5395B-A15668-GM replaces three discrete clock ICs, simplifying layout and ensuring deterministic skew across 12 parallel SerDes lanes.

Use Scenario: Timing engine for high-resolution MRI and PET scanner front-end digitizers requiring sub-picosecond jitter stability.

IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer generating 125 MHz, 250 MHz, and 500 MHz sampling clocks from a 10 MHz OCXO reference.

Use Value: 71 fs jitter directly translates to <0.05 LSB noise floor degradation in 16-bit ADCs, preserving image SNR and spatial resolution.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5395A-A-GM	Same 64-QFN package and 4-in/12-out topology, but supports full 0.0001–1028 MHz output range with integer+fractional synthesis; 69 fs jitter (Grade P).	Targeted at highest-performance 56G PAM4 designs where 69 fs is mandatory; lacks SI5395B-A15668-GM's optimized 0.0001–350 MHz range and lower-cost Grade B qualification.	Select SI5395A-A-GM only if full-bandwidth synthesis and sub-71 fs jitter are required; otherwise SI5395B-A15668-GM offers cost-optimized performance for sub-350 MHz SyncE and OTN use cases.
SI5345B-D-GM	Third-generation DSPLL; 12-output, 64-QFN, but limited to 0.0001–350 MHz output and 115 fs jitter; no integrated holdover history buffer or ramped holdover exit.	Legacy drop-in replacement for existing Si534x-based designs; lacks G.8262.1 eEEC compliance and enhanced hitless switching of SI5395B-A15668-GM.	Choose SI5345B-D-GM only for backward-compatible upgrades where G.8262.1 compliance and <75 fs jitter are not required; SI5395B-A15668-GM adds critical next-gen timing features.

Compared with SI5395A-A-GM, SI5395B-A15668-GM trades 2 fs of jitter for tighter 350 MHz output band and Grade B qualification-reducing cost while retaining full pin compatibility and holdover intelligence. Against SI5345B-D-GM, it delivers 44 fs less jitter, adds G.8262.1 compliance, and enables ramped holdover exit-making it essential for new 100G+ infrastructure designs.

Availability

SI5395B-A15668-GM is available at Aetrix Electronics and suitable for 100G/400G networking line cards, OTN transponders, and 56G PAM4 SerDes clocking requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5395B-A15668-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The SI5395B-A15668-GM belongs to Skyworks' Si5395 family of any-frequency jitter attenuators, designed specifically for carrier-grade synchronization in 5G transport, cloud data center networking, and high-performance test equipment.

FAQ

What is the reference clock requirement for SI5395B-A15668-GM?

The SI5395B-A15668-GM requires a 48–54 MHz fundamental-mode crystal connected to XA/XB pins, per Skyworks' Grade B specification. Internal load capacitors eliminate external components. For SyncE pizza-box applications demanding ultra-low wander, a TCXO is recommended instead of a crystal. The SI5395B-A15668-GM does not support integrated reference operation - it is an external-reference-only Grade B device.

Does SI5395B-A15668-GM support hitless switching between arbitrary input frequencies?

SI5395B-A15668-GM supports enhanced hitless switching only between input clocks that are frequency-locked - i.e., identical or integer-related frequencies (e.g., 25 MHz and 125 MHz). It does not perform hitless switching between unrelated frequencies like 8 kHz and 155.52 MHz. Phase transients remain ≤0.2 ns for qualifying pairs, as verified in Skyworks AN1151 and the Si5395 Family Reference Manual.

Can SI5395B-A15668-GM generate both LVDS and LVCMOS outputs simultaneously?

Yes. SI5395B-A15668-GM supports simultaneous LVDS, LVPECL, LVCMOS, CML, and HCSL outputs across its 12 pins, with independent programmable amplitude and termination per output. Each output is routed through an internal crosspoint switch and driven by a dedicated MultiSynth, enabling mixed-format clock trees - for example, LVDS for SerDes and LVCMOS for FPGA configuration - from a single SI5395B-A15668-GM device.

What is the maximum output frequency supported by SI5395B-A15668-GM?

The SI5395B-A15668-GM supports differential output frequencies up to 1028 MHz and LVCMOS outputs up to 250 MHz, as specified in Skyworks' April 2025 Final Data Sheet (Section 1, Feature List). This range covers all standard SyncE (156.25 MHz), OTN (155.52/622.08 MHz), and 100G KR4/CR4 SerDes (103.125 GHz ÷ 64 = 1.611 GHz → not supported; but 103.125 GHz ÷ 128 = 805.66 MHz → supported) requirements.

How is holdover behavior configured in SI5395B-A15668-GM?

Holdover behavior in SI5395B-A15668-GM is configured via registers controlling the historical data window (1–120 seconds), delay before failure (to exclude corrupted pre-failure samples), and ramp rate on exit (0.2–40,000 ppm/s). These parameters are set using ClockBuilder Pro software and stored in NVM. The device automatically enters holdover upon loss of all valid inputs and exits glitchlessly when a new input qualifies - all verified in Section 4.4.5 of the Si5395 Family Reference Manual.

SI5395B-A15668-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL™, MultiSynth™

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: -

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: Clock, Crystal, LVCMOS

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5395B-A15668-GM FAQ

1.How can I place an order for SI5395B-A15668-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5395B-A15668-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5395B-A15668-GM reliable?

The price and inventory of SI5395B-A15668-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5395B-A15668-GM is usually 5 days.

3.What payment methods are accepted for SI5395B-A15668-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5395B-A15668-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5395B-A15668-GM?

SI5395B-A15668-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5395B-A15668-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5395B-A15668-GM?

For technical support, including SI5395B-A15668-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5395B-A15668-GM requirements.

6.How does Aetrix verify that SI5395B-A15668-GM is sourced from the original manufacturer or authorized distributors?

All SI5395B-A15668-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5395B-A15668-GM meets industry standards.

7.What is the process for return or replacement of SI5395B-A15668-GM?

All SI5395B-A15668-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5395B-A15668-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5395B-A15668-GM part is unused and in its original packaging.

Return procedure for SI5395B-A15668-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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