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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5395B-A15728-GM

Name: SI5395B-A15728-GM
Brand: Skyworks Solutions Inc.
SKU: SI5395B-A15728-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5395B-A15728-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5395B-A15728-GM.pdf

Description:: SINGLE PLL JITTER ATTENUATOR WIT

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5395B-A15728-GM from Skyworks Solutions is a fourth-generation DSPLL®-based jitter attenuator and clock multiplier IC with 4 differential/LVCMOS inputs and 12 programmable outputs, delivering 71 fs RMS phase jitter (Grade E), 0.1 Hz–4 kHz configurable loop bandwidth, and ultra-low-jitter clock synthesis from 100 Hz to 1028 MHz for 56G/112G PAM4 SerDes systems.

For engineers reviewing the SI5395B-A15728-GM datasheet, SI5395B-A15728-GM pinout, SI5395B-A15728-GM application, or SI5395B-A15728-GM equivalent, this device supports hitless switching between gapped or integer-related clocks, integrated status monitoring (LOS/OOF/LOL), and in-circuit NVM programming via I²C/SPI - critical for SyncE line cards, OTN transponders, and medical imaging timing subsystems.

Technical Context

The SI5395B-A15728-GM implements a digitally controlled oscillator (DCO) architecture with fractional input dividers (P), MultiSynth™ frequency synthesizers (N), and programmable integer output dividers (R), enabling any-output-frequency generation from any-input-frequency within its 8 kHz–750 MHz input range. Its DSPLL loop bandwidth is user-configurable from 0.1 Hz to 4 kHz for precise jitter attenuation tuning.

It operates in free-run, locked, holdover, and enhanced hitless switching modes, with programmable holdover averaging over up to 120 s of historical frequency data and ramped holdover exit using selectable rates from 0.2 ppm/s to 40,000 ppm/s. The device uses an external crystal reference (48–54 MHz) and supports LVDS, LVPECL, LVCMOS, CML, and HCSL output formats with independent voltage supply pins (1.8 V/2.5 V/3.3 V).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	71 fs - meets ITU-T G.8262.1 eEEC requirements for Enhanced SyncE applications
Input Frequency Range	8 kHz–750 MHz differential - supports legacy telecom clocks (8 kHz), SerDes references (19.44/25 MHz), and high-speed interfaces
Output Frequency Range	100 Hz–1028 MHz differential - covers baseband, Ethernet, OTN, and PAM4 SerDes clocking needs
DSPLL Loop Bandwidth	0.1 Hz–4 kHz programmable - enables precise trade-off between jitter attenuation and transient response
Output Count & Type	12 differential outputs - supports multi-domain clock distribution with independent format/voltage configuration
Reference Source	External crystal (48–54 MHz) - eliminates need for external load capacitors and reduces board-level noise coupling
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - ensures stable core and analog operation across industrial temperature range

Pinout & Package

SI5395B-A15728-GM is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5395 Family Reference Manual (Rev. 1.4) and datasheet Figure 1.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Accept primary timing references; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT11	Differential clock outputs	Programmable format (LVDS/LVPECL/CML/HCSL/LVCMOS); each with independent voltage supply (VDDOx)
XA/XB	Crytal oscillator interface	Connects to 48–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA	I²C serial interface	Two-wire control bus for configuration, status readback, and NVM programming
SCLK/MOSI/MISO/SSN	SPI serial interface	Alternative 4-wire interface supporting faster register access and bulk configuration
RSTb	Hardware reset input	Active-low signal initiating full initialization and NVM reload - required before functional operation
LOL	Loss-of-Lock indicator	Open-drain output asserting when DSPLL exits locked mode - used for system fault detection

Key Features

Feature	Design Value
Enhanced hitless switching	0.2 ns typical output phase transient during switch between integer-related inputs (e.g., 25 MHz ↔ 25 MHz)
Programmable holdover averaging	Configurable 1–120 s history window and delay offset to reject corrupted pre-failure frequency samples
Frequency-on-the-fly (FOTF)	Independent MultiSynth reconfiguration without disrupting other outputs - enables dynamic rate adaptation
Digital Controlled Oscillator (DCO) mode	0.001 ppb step size for fine-grained frequency adjustment in free-run or locked mode
Status monitoring	Real-time detection of Loss-of-Signal (LOS), Out-of-Frequency (OOF), and Loss-of-Lock (LOL) on all inputs/outputs

Applications

56G/112G PAM4 SerDes Clocking	OTN Muxponders & Transponders
Use Scenario: Generating ultra-low-jitter reference clocks for 56G/112G PAM4 SerDes PHYs in AI accelerators and optical modules. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier providing sub-100 fs RMS phase noise to meet IEEE 802.3cd BER requirements. Use Value: Enables reliable 56G PAM4 link establishment with <1e-12 BER at 100+ m over backplanes by suppressing input jitter from PLLs or recovered clocks.	Use Scenario: Synchronizing multiple OTN framers and mapping engines in metro/core transport systems. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 155.52 MHz, 622.08 MHz, and 2.488 GHz from a common 8 kHz or 19.44 MHz reference. Use Value: Eliminates external frequency translators and reduces BOM count while meeting ITU-T G.8262 EEC Option 1/2 wander specifications.
100/400G Synchronous Ethernet Line Cards	Medical Imaging Timing Subsystems
Use Scenario: Providing traceable, phase-aligned clocks across distributed FPGA-based packet processing pipelines in SyncE-compliant line cards. IC Role / Device Role / Timing Role: Hitless-switching jitter cleaner maintaining phase continuity during reference switchover between primary and backup BITS sources. Use Value: Ensures zero-packet-loss failover and meets ITU-T G.8262.1 eEEC holdover stability (<±4.6 ppm over 24 h) without external TCXO.	Use Scenario: Distributing precisely timed trigger and sampling clocks across MRI gradient coil drivers and ADC arrays. IC Role / Device Role / Timing Role: Low-phase-noise clock generator synchronizing RF excitation pulses and echo acquisition windows with sub-nanosecond alignment. Use Value: Reduces image ghosting and improves spatial resolution by minimizing timing skew between parallel receive channels.

56G/112G PAM4 SerDes Clocking

OTN Muxponders & Transponders

Use Scenario: Generating ultra-low-jitter reference clocks for 56G/112G PAM4 SerDes PHYs in AI accelerators and optical modules.

IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier providing sub-100 fs RMS phase noise to meet IEEE 802.3cd BER requirements.

Use Value: Enables reliable 56G PAM4 link establishment with <1e-12 BER at 100+ m over backplanes by suppressing input jitter from PLLs or recovered clocks.

Use Scenario: Synchronizing multiple OTN framers and mapping engines in metro/core transport systems.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 155.52 MHz, 622.08 MHz, and 2.488 GHz from a common 8 kHz or 19.44 MHz reference.

Use Value: Eliminates external frequency translators and reduces BOM count while meeting ITU-T G.8262 EEC Option 1/2 wander specifications.

100/400G Synchronous Ethernet Line Cards

Medical Imaging Timing Subsystems

Use Scenario: Providing traceable, phase-aligned clocks across distributed FPGA-based packet processing pipelines in SyncE-compliant line cards.

IC Role / Device Role / Timing Role: Hitless-switching jitter cleaner maintaining phase continuity during reference switchover between primary and backup BITS sources.

Use Value: Ensures zero-packet-loss failover and meets ITU-T G.8262.1 eEEC holdover stability (<±4.6 ppm over 24 h) without external TCXO.

Use Scenario: Distributing precisely timed trigger and sampling clocks across MRI gradient coil drivers and ADC arrays.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator synchronizing RF excitation pulses and echo acquisition windows with sub-nanosecond alignment.

Use Value: Reduces image ghosting and improves spatial resolution by minimizing timing skew between parallel receive channels.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-A-GM	Legacy 3rd-gen DSPLL; 115 fs RMS jitter; fixed 100 Hz loop bandwidth; no FOTF or ramped holdover exit	Limited to lower-speed SerDes (28G) and legacy SyncE; lacks programmable holdover averaging	Select only if cost-sensitive and jitter >100 fs acceptable; not suitable for 56G PAM4 or eEEC compliance
LMK04832ISQE/NOPB	TI dual-loop jitter cleaner; 90 fs RMS; supports JESD204B deterministic latency; no integrated crystal option	Better suited for JESD204B converter timing; requires external VCXO for holdover; higher power consumption	Prefer when deterministic latency or JESD204B SYSREF alignment is required; avoid if board space or crystal integration is critical

Compared with Si5345B-A-GM and LMK04832ISQE/NOPB, the SI5395B-A15728-GM delivers 42 fs lower jitter than the Si5345B, adds programmable holdover averaging and ramped exit for improved resilience, and integrates crystal loading - making it optimal for next-gen 56G/112G infrastructure where phase continuity and compact timing solutions are mandatory.

Availability

SI5395B-A15728-GM is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder synchronization, and Synchronous Ethernet line card designs requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for SI5395B-A15728-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies for infrastructure, automotive, and industrial markets.

The SI5395B-A15728-GM belongs to Skyworks' Si539x family of any-frequency jitter attenuators, engineered specifically for ultra-low-jitter clock generation in high-speed networking, optical transport, and precision instrumentation applications demanding sub-100 fs phase noise and robust holdover performance.

FAQ

What is the phase jitter specification for SI5395B-A15728-GM?

The SI5395B-A15728-GM achieves 71 fs RMS phase jitter (integrated from 12 kHz to 20 MHz) in Grade E configuration, verified per Skyworks Final Data Sheet 206689B. This value applies when using a 48–54 MHz external crystal reference and operating in locked mode with optimized loop bandwidth settings - meeting ITU-T G.8262.1 eEEC requirements for Enhanced SyncE systems.

Does SI5395B-A15728-GM support hitless switching between non-integer-related input clocks?

No, SI5395B-A15728-GM requires input clocks to be either identical in frequency or related by an exact integer ratio (e.g., 25 MHz ↔ 50 MHz) for hitless switching. For non-integer-related inputs, the device performs ramped switching or standard lock-acquisition - both introducing measurable phase transients. The datasheet specifies 0.2 ns typical phase transient only for integer-related hitless transitions.

Can SI5395B-A15728-GM operate without an external crystal?

No - SI5395B-A15728-GM belongs to the A/B/C/D/P grade group and requires an external 48–54 MHz fundamental-mode crystal connected to XA/XB pins. It does not include an integrated resonator. Using an external XO or REFCLK is possible but degrades jitter performance; crystal connection is mandatory for achieving the specified 71 fs RMS phase jitter.

How many output formats does SI5395B-A15728-GM support per channel?

SI5395B-A15728-GM supports five programmable output formats per channel: LVDS, LVPECL, LVCMOS, CML, and HCSL. Each of the 12 outputs can be independently configured for format, amplitude, and drive strength via register settings. Format selection is done per-output and does not require shared resources or multiplexing constraints.

Is SI5395B-A15728-GM pin-compatible with earlier Si5345 variants?

Yes - SI5395B-A15728-GM is drop-in compatible with Si5345B-A-GM per Skyworks AN1155. Both use the same 64-QFN 9×9 mm package, identical pinout, and share register map compatibility for basic configuration. However, advanced features like FOTF, ramped holdover exit, and programmable holdover averaging require updated firmware and ClockBuilder Pro v3.0+.

SI5395B-A15728-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: -

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: Clock, Crystal, LVCMOS

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5395B-A15728-GM FAQ

1.How can I place an order for SI5395B-A15728-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5395B-A15728-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5395B-A15728-GM reliable?

The price and inventory of SI5395B-A15728-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5395B-A15728-GM is usually 5 days.

3.What payment methods are accepted for SI5395B-A15728-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5395B-A15728-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5395B-A15728-GM?

SI5395B-A15728-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5395B-A15728-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5395B-A15728-GM?

For technical support, including SI5395B-A15728-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5395B-A15728-GM requirements.

6.How does Aetrix verify that SI5395B-A15728-GM is sourced from the original manufacturer or authorized distributors?

All SI5395B-A15728-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5395B-A15728-GM meets industry standards.

7.What is the process for return or replacement of SI5395B-A15728-GM?

All SI5395B-A15728-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5395B-A15728-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5395B-A15728-GM part is unused and in its original packaging.

Return procedure for SI5395B-A15728-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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