Skyworks Solutions Inc. SI5395L-A-GM

Overview

SI5395L-A-GM from Skyworks Solutions is a 4-input, 12-output ultra-low-jitter clock multiplier and jitter attenuator with integrated crystal reference, supporting integer-only frequency synthesis up to 1028 MHz differential output, 69–85 fs RMS phase jitter, and operation in free-run, locked, and holdover modes for telecom and high-speed SerDes applications.

For engineers reviewing the SI5395L-A-GM datasheet, SI5395L-A-GM pinout, SI5395L-A-GM application, or SI5395L-A-GM equivalent, this device delivers deterministic hitless switching, programmable DSPLL loop bandwidth (0.1 Hz–4 kHz), G.8262/G.8262.1 compliance, and ClockBuilder Pro–enabled configuration for 56G/112G PAM4, OTN, and SyncE line cards.

Technical Context

The SI5395L-A-GM implements a fourth-generation DSPLL architecture with on-chip MultiSynth dividers, enabling integer-mode synthesis across all 12 outputs while maintaining 85 fs RMS jitter. Its integrated crystal oscillator eliminates external XTAL components and acoustic noise sensitivity, and supports enhanced hitless switching between input clocks with fixed phase relationships.

It operates in four defined modes-free-run, lock acquisition, locked, and holdover-with programmable holdover history (up to 120 s) and ramped exit (0.2–40,000 ppm/s). The device uses I²C/SPI for configuration and stores settings in on-chip OTP NVM, ensuring known-state power-up without external programming.

Key Specifications

Pinout & Package

SI5395L-A-GM is housed in a 64-pin LGA package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5395 Family Reference Manual (Rev. 1.4, Section 5.2) and validated for this exact grade (L) and package variant (LGA).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator and clock multiplier applications.

Compared with SI5395C-A-GM, SI5395L-A-GM saves board space and improves reliability via integrated crystal; compared with SI5395J-A-GM, it trades fractional flexibility for lower EMI risk and simpler validation in integer-only deployments like SyncE line cards.

Availability

SI5395L-A-GM is available at Aetrix Electronics and suitable for 56G SerDes clocking, OTN transponder timing, and Synchronous Ethernet line card designs requiring stable component supply, long-term lifecycle assurance, and RoHS-6 compliance.

Supply support for SI5395L-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5395 family is designed for high-performance timing in optical networking, data center interconnects, and telecom infrastructure - delivering ultra-low jitter, multi-input redundancy, and standards-compliant holdover for mission-critical synchronization.

FAQ

What is the reference architecture used in the SI5395L-A-GM?

The SI5395L-A-GM uses a fourth-generation DSPLL (Digital Synthesizer Phase-Locked Loop) with integrated MultiSynth dividers and an on-die crystal oscillator. Unlike external-reference variants, its Grade L configuration relies entirely on the internal resonator for free-run and holdover stability - eliminating XTAL placement, load capacitor tuning, and acoustic noise coupling risks. This architecture achieves 85 fs RMS jitter in integer mode and supports programmable loop bandwidth from 0.1 Hz to 4 kHz.

Does the SI5395L-A-GM support fractional frequency synthesis?

No, the SI5395L-A-GM supports integer-only frequency synthesis only. This is explicitly specified in Table 3 of the Skyworks Final Data Sheet for J/K/L/M/E grades: "Si5395L-A-GM1,2 - Integer Only". Fractional synthesis is available in other variants like SI5395J-A-GM, but SI5395L-A-GM omits fractional-N capability to reduce spurious emissions, simplify EMI filtering, and ensure deterministic jitter performance for SyncE and SerDes applications where integer ratios dominate.

What package type and footprint does the SI5395L-A-GM use?

The SI5395L-A-GM uses a 64-pin LGA (Land Grid Array) package measuring 9 × 9 mm with 0.5 mm pitch and an exposed thermal pad. This matches the "64-LGA" designation in Skyworks' Ordering Guide (Table 3) for integrated-reference Si5395 variants. It is not pin-compatible with the 64-QFN variant (e.g., SI5395A-A-GM), which uses a different land pattern, solder stencil design, and thermal vias strategy - requiring separate PCB layout and assembly validation.

How does the SI5395L-A-GM handle input clock failure?

Upon input clock failure, the SI5395L-A-GM automatically enters holdover mode using its integrated crystal reference. It calculates a final holdover frequency from up to 120 seconds of stored historical input frequency data, applying a user-programmable averaging window to minimize phase disturbance. Output frequency drift during holdover depends solely on the stability of the internal crystal - typically ±50 ppm over temperature - and meets ITU-T G.8262.1 eEEC requirements for telecom infrastructure timing resilience.

Can the SI5395L-A-GM be configured without external programming hardware?

Yes, the SI5395L-A-GM includes on-chip one-time-programmable (OTP) non-volatile memory that stores factory- or user-defined configurations. After initial programming via I²C or SPI using ClockBuilder Pro software, the device powers up with fully operational clocks without host intervention. This eliminates boot-time dependencies on microcontrollers or FPGA configuration logic - critical for systems requiring immediate timing availability after cold start or reset.