Skyworks Solutions Inc. SI5396B-A-GMR

Overview

SI5396B-A-GMR from Skyworks Solutions is a dual-DSPLL jitter attenuator with four outputs, designed for telecom and datacom timing systems requiring ultra-low jitter (95 fs rms), independent frequency synthesis, and hitless clock switching. It supports differential inputs up to 750 MHz and LVCMOS inputs up to 250 MHz, delivering programmable output frequencies from 100 Hz to 350 MHz in LVDS/LVPECL/LVCMOS/CML/HCSL formats - deployed in Synchronous Ethernet line cards and 10/25/100G Carrier Ethernet switches.

For engineers reviewing the SI5396B-A-GMR datasheet, SI5396B-A-GMR pinout, SI5396B-A-GMR application, or SI5396B-A-GMR equivalent, key selection criteria include its 2-DSPLL architecture, integrated reference-free operation (Grade A/B uses external crystal), 44-QFN 7×7 mm package, and support for automatic holdover, frequency-on-the-fly reconfiguration, and gapped-clock synchronization - all critical for carrier-grade PLL design and OTN timing recovery.

Technical Context

The SI5396B-A-GMR implements two independent fourth-generation DSPLLs, each with configurable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter attenuation per timing domain. Each DSPLL accesses any of four differential or LVCMOS inputs (IN0–IN3) via flexible crosspoint routing and drives up to four outputs with programmable format, amplitude, and supply voltage (1.8/2.5/3.3 V).

It operates in Free-run, Locked, Holdover, and Lock Acquisition modes, with Fastlock acceleration for rapid lock acquisition and DCO-mode frequency stepping down to 0.01 ppb. Status monitoring includes LOS, OOF, and LOL detection on all inputs and per-DSPLL outputs - essential for ITU-T G.8262-compliant SyncE applications.

Key Specifications

Pinout & Package

SI5396B-A-GMR is housed in a 44-pin QFN package (7×7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5396 Family Reference Manual and confirmed for Grade A/B variants.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5396B-A-GMR, Si5396A-A-GMR extends output frequency capability for next-gen SerDes, while Si5346B-D-GM trades jitter performance and configurability for legacy compatibility and lower BOM cost - making SI5396B-A-GMR the optimal balance for carrier-class SyncE and OTN timing where 350 MHz coverage and 95 fs jitter are mandatory.

Availability

SI5396B-A-GMR is available at Aetrix Electronics and suitable for Synchronous Ethernet line cards, OTN muxponders, broadcast video routers, and 5G fronthaul gateways requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5396B-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5396B-A-GMR belongs to Skyworks' DSPLL® jitter attenuator product line, engineered for carrier-grade timing in telecom infrastructure - delivering ultra-low jitter, multi-domain synchronization, and robust holdover for SyncE, OTN, and IEEE 1588 applications.

FAQ

What is the reference clock requirement for SI5396B-A-GMR?

The SI5396B-A-GMR requires an external 48–54 MHz fundamental-mode crystal connected to XA/XB pins. Internal load capacitors eliminate external components. For SyncE holdover stability, a TCXO is recommended; standard crystals provide ±100 ppm freerun accuracy. The SI5396B-A-GMR does not support integrated reference - that functionality is reserved for Grades J/K/L/M.

Does SI5396B-A-GMR support hitless switching between asynchronous clocks?

No - SI5396B-A-GMR supports hitless switching only between frequency-locked inputs (e.g., integer-related or identical frequencies like dual 155.52 MHz SyncE sources). For asynchronous clocks differing by up to ±500 ppm, it performs glitchless switching using Fastlock or DSPLL loop bandwidth pull-in - ensuring no runt pulses but allowing controlled phase transient.

Can SI5396B-A-GMR generate both LVDS and LVCMOS outputs simultaneously?

Yes - SI5396B-A-GMR supports mixed-format outputs: OUT0–OUT3 can be independently configured as LVDS, LVPECL, LVCMOS, CML, or HCSL. Each output has dedicated VDDO supply pins (1.8/2.5/3.3 V), enabling concurrent LVDS (2.5 V) and LVCMOS (1.8 V) generation without level shifters - critical for interfacing with heterogeneous ASIC/FPGA I/O banks.

What is the maximum input frequency SI5396B-A-GMR accepts on LVCMOS inputs?

The SI5396B-A-GMR accepts LVCMOS input frequencies from 8 kHz to 250 MHz on IN0–IN3. This range covers common telecom references (e.g., 10 MHz GPSDO, 155.52 MHz SyncE, 125 MHz Ethernet) and video clocks (e.g., 27 MHz SDI, 74.25 MHz 3G-SDI). Differential inputs extend to 750 MHz for high-speed SerDes recovery.

How does SI5396B-A-GMR handle loss of all input references?

When all four inputs (IN0–IN3) fail, each DSPLL in SI5396B-A-GMR automatically enters Holdover Mode using averaged historical frequency data (up to 120 s stored). The final holdover frequency is calculated from a programmable window within that history - minimizing phase disturbance. Output stability then depends solely on the external crystal's aging and temperature drift.