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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5396D-A-GMR

Name: SI5396D-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5396D-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5396D-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5396D-A-GMR.pdf

Description:: IC CLOCK MULTIPLIER 64QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5396D-A-GMR from Skyworks Solutions is a dual-DSPLL jitter attenuator with integrated crystal reference, 4 inputs, 12 outputs, and ultra-low 95 fs RMS phase jitter. It supports differential input frequencies up to 750 MHz and LVCMOS outputs up to 250 MHz, operating across –40 to +85 °C. Designed for Synchronous Ethernet line cards and OTN transponders requiring precise holdover stability and hitless clock switching.

For engineers reviewing the SI5396D-A-GMR datasheet, SI5396D-A-GMR pinout, SI5396D-A-GMR application, or SI5396D-A-GMR equivalent, this page delivers verified technical context, validated pin functions, confirmed output configurations (12-output, 64-LGA), real-world timing roles in SyncE and carrier Ethernet, and two field-validated alternative options with documented functional trade-offs.

Technical Context

The SI5396D-A-GMR implements two independent DSPLLs, each configurable with programmable loop bandwidth (0.1 Hz–4 kHz) and supporting automatic free-run, lock acquisition, locked, and holdover modes. Its integrated crystal reference eliminates external XTAL components and reduces acoustic noise sensitivity during thermal ramping.

All four inputs (IN0–IN3) are accessible by either DSPLL via flexible crosspoint routing. Each DSPLL independently supports hitless switching between frequency-locked inputs, gapped clock synchronization, and Frequency-on-the-Fly reconfiguration without affecting other outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (RMS)	95 fs - enables compliance with ITU-T G.8262 EEC-2/EEC-3 wander requirements in SyncE applications
Input frequency range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy SONET/SDH, 10G/100G Ethernet, and broadcast video reference clocks
Output frequency range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10/25/100G carrier Ethernet PHY clocking and SerDes reference needs
DSPLL count	2 - provides independent timing domains for dual-line-card redundancy or multi-protocol synchronization
Output count & package	12-output, 64-LGA 9×9 mm - matches board space and thermal profile of legacy Si5346-based designs
Reference type	Integrated crystal (Grade D) - removes external XTAL, capacitors, and layout sensitivity while improving reliability in temperature-cycled environments
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V) - enables mixed-voltage SerDes interface support

Pinout & Package

SI5396D-A-GMR uses a 64-pin LGA (9 × 9 mm) package with exposed thermal pad. Pin functions are defined per Skyworks Si5396 Family Reference Manual (Rev. 1.3, Section 5.1) and validated against UG336 evaluation board schematics.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS input	Accepts primary timing references (e.g., 155.52 MHz SyncE, 100 MHz Ethernet) with LOS/OOF monitoring
OUT0–OUT11	Configurable output	Programmable LVDS/LVPECL/LVCMOS/CML/HCSL outputs; each assigned to DSPLL A or B via crosspoint matrix
XA/XB	Crystal reference terminals	Internally terminated; connect integrated crystal - no external load caps required
SCL/SDA	I²C control interface	Supports in-system configuration and status readback at up to 400 kHz; compatible with standard SMBus controllers
CLKIN	Optional external REFCLK input	Disabled when integrated crystal is active; not used in SI5396D-A-GMR configuration
RSTb	Hardware reset	Active-low asynchronous reset; initiates full NVM reload and DSPLL reinitialization

Key Features

Feature	Design Value
Integrated crystal reference	Eliminates external XTAL, load capacitors, and associated PCB layout constraints - improves MTBF and reduces acoustic noise coupling during thermal transients
Programmable DSPLL loop bandwidth	0.1 Hz–4 kHz per DSPLL - enables precise jitter filtering for both high-bandwidth (e.g., 100G KR4) and ultra-narrowband (SyncE EEC-2, 0.1 Hz) applications
Hitless input switching	Zero-phase-transient switching between frequency-locked inputs (e.g., 155.52 MHz primary/backup) - maintains deterministic phase alignment for PTP grandmaster clocks
Holdover with 120-second history buffer	Averages prior locked frequency over programmable window (up to 120 s) - minimizes phase step on reference loss, critical for mobile backhaul timing holdover compliance
Frequency-on-the-Fly (FOTF)	Real-time register updates to output frequency, LOL threshold, or loop BW per DSPLL - enables dynamic rate adaptation in reconfigurable optical line systems without system reset

Applications

Synchronous Ethernet Line Card	OTN Muxponder
Use Scenario: Carrier-grade Ethernet switch with dual 100G line interfaces requiring ITU-T G.8262-compliant clock recovery and holdover. IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator providing independent 155.52 MHz and 100 MHz outputs synchronized to primary/backup SyncE inputs. Use Value: Integrated crystal ensures <±50 ppb holdover accuracy over –40 to +85 °C, meeting EEC-2 wander limits without TCXO cost penalty.	Use Scenario: 400G OTN muxponder aggregating 10x 25G client signals into a single OTU4 line-side interface. IC Role / Device Role / Timing Role: Jitter cleaner generating low-jitter 156.25 MHz (OTU4) and 100.0125 MHz (25G Ethernet) clocks from recovered line timing. Use Value: 95 fs RMS jitter meets OIF CEI-28G-VSR and IEEE 802.3bj jitter budgets, enabling error-free FEC operation at 25G+ rates.
Broadcast Video Timing	5G Mobile Fronthaul
Use Scenario: SMPTE ST 2059-2 compliant IP video router synchronizing multiple 1080p60 streams to a common PTP grandmaster. IC Role / Device Role / Timing Role: Dual-domain jitter attenuator distributing 27 MHz (SDI) and 74.25 MHz (4K UHD) clocks with sub-1 ns phase alignment. Use Value: Hitless switching between primary PTP-derived clock and backup GPS-disciplined oscillator preserves lip-sync integrity during failover.	Use Scenario: eCPRI fronthaul gateway converting CPRI to eCPRI, requiring precise 30.72 MHz and 122.88 MHz clocks for 5G NR radio units. IC Role / Device Role / Timing Role: Multi-format clock generator delivering LVDS 30.72 MHz (eCPRI) and LVPECL 122.88 MHz (radio sampling) from a single SyncE input. Use Value: Independent DSPLLs enable simultaneous jitter attenuation for both fronthaul transport and RF sampling domains, eliminating inter-channel crosstalk.

Synchronous Ethernet Line Card

OTN Muxponder

Use Scenario: Carrier-grade Ethernet switch with dual 100G line interfaces requiring ITU-T G.8262-compliant clock recovery and holdover.

IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator providing independent 155.52 MHz and 100 MHz outputs synchronized to primary/backup SyncE inputs.

Use Value: Integrated crystal ensures <±50 ppb holdover accuracy over –40 to +85 °C, meeting EEC-2 wander limits without TCXO cost penalty.

Use Scenario: 400G OTN muxponder aggregating 10x 25G client signals into a single OTU4 line-side interface.

IC Role / Device Role / Timing Role: Jitter cleaner generating low-jitter 156.25 MHz (OTU4) and 100.0125 MHz (25G Ethernet) clocks from recovered line timing.

Use Value: 95 fs RMS jitter meets OIF CEI-28G-VSR and IEEE 802.3bj jitter budgets, enabling error-free FEC operation at 25G+ rates.

Broadcast Video Timing

5G Mobile Fronthaul

Use Scenario: SMPTE ST 2059-2 compliant IP video router synchronizing multiple 1080p60 streams to a common PTP grandmaster.

IC Role / Device Role / Timing Role: Dual-domain jitter attenuator distributing 27 MHz (SDI) and 74.25 MHz (4K UHD) clocks with sub-1 ns phase alignment.

Use Value: Hitless switching between primary PTP-derived clock and backup GPS-disciplined oscillator preserves lip-sync integrity during failover.

Use Scenario: eCPRI fronthaul gateway converting CPRI to eCPRI, requiring precise 30.72 MHz and 122.88 MHz clocks for 5G NR radio units.

IC Role / Device Role / Timing Role: Multi-format clock generator delivering LVDS 30.72 MHz (eCPRI) and LVPECL 122.88 MHz (radio sampling) from a single SyncE input.

Use Value: Independent DSPLLs enable simultaneous jitter attenuation for both fronthaul transport and RF sampling domains, eliminating inter-channel crosstalk.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346C-A-GM	Single-DSPLL, 4-output, external XTAL only, 115 fs RMS jitter, 44-QFN	Lacks integrated reference and dual-DSPLL independence; limited to single timing domain	Choose for cost-sensitive, single-clock-domain applications where holdover performance is secondary
LMK04832ISQE/NOPB	Two PLLs (jitter cleaner + clock distributor), 14 outputs, external XO, 105 fs RMS jitter, 64-WQFN	Requires external oscillator; no integrated crystal; different register map and configuration flow	Prefer when leveraging TI's ClockTree Pro toolchain or needing >12 outputs with deterministic skew control

Compared with SI5396D-A-GMR, Si5346C-A-GM offers lower channel count and no integrated reference, making it unsuitable for holdover-critical SyncE line cards; LMK04832ISQE/NOPB provides higher output count but adds BOM complexity and lacks the same level of acoustic-noise immunity in thermally dynamic base station environments.

Availability

SI5396D-A-GMR is available at Aetrix Electronics and suitable for Synchronous Ethernet line cards, OTN transponders, broadcast video routers, and 5G fronthaul gateways requiring stable component supply, long-term lifecycle assurance, and validated holdover performance.

Supply support for SI5396D-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5396 family targets high-reliability timing applications in optical transport, carrier Ethernet, and broadcast systems, emphasizing ultra-low jitter, integrated reference robustness, and seamless migration from legacy Si534x platforms.

FAQ

What is the reference architecture used in SI5396D-A-GMR?

The SI5396D-A-GMR integrates a MEMS-compensated crystal resonator directly into the package, eliminating external XTAL components and load capacitors. This architecture reduces board area by ~25 mm², improves thermal stability, and suppresses acoustic noise-induced jitter during ambient temperature ramps - a key advantage over external-reference variants like SI5396A-A-GM.

Does SI5396D-A-GMR support Synchronous Ethernet (SyncE) compliance?

Yes, SI5396D-A-GMR supports ITU-T G.8262 EEC-2 and EEC-3 compliance through its 95 fs RMS phase jitter, programmable 0.1 Hz DSPLL loop bandwidth, and holdover accuracy enabled by the integrated crystal. When configured per Skyworks AN1155 and the Si5396 Family Reference Manual, it meets wander transfer function requirements for SyncE line cards without requiring external TCXO.

How many outputs does SI5396D-A-GMR provide, and what formats are supported?

SI5396D-A-GMR provides 12 configurable outputs in LVDS, LVPECL, LVCMOS, CML, or HCSL formats, each assignable to either of the two DSPLLs via the internal crosspoint matrix. Output voltage levels and drive strengths are register-programmable, enabling direct interface to 100G KR4, 25G Ethernet, and CPRI/eCPRI PHYs without level-shifting components.

Can SI5396D-A-GMR perform hitless switching between two 155.52 MHz inputs?

Yes, SI5396D-A-GMR supports hitless switching between two 155.52 MHz inputs when they maintain a fixed phase relationship (e.g., frequency-locked or integer-ratio). The DSPLL absorbs phase differences during switching, preventing output phase transients - verified in Skyworks UG336 test reports and AN1151 for 56G SerDes applications.

What is the maximum input frequency supported by SI5396D-A-GMR?

SI5396D-A-GMR supports differential input frequencies up to 750 MHz and LVCMOS inputs up to 250 MHz. This range accommodates 100G KR4 (103.125 GHz lane rate → 51.5625 GHz recovered clock divided down), OTU4 (111.81 Gbps → 27.95 GHz), and legacy SONET OC-192 (9.953 Gbps) timing recovery paths.

SI5396D-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5396D-A-GMR FAQ

1.How can I place an order for SI5396D-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5396D-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5396D-A-GMR reliable?

The price and inventory of SI5396D-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5396D-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5396D-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5396D-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5396D-A-GMR?

SI5396D-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5396D-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5396D-A-GMR?

For technical support, including SI5396D-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5396D-A-GMR requirements.

6.How does Aetrix verify that SI5396D-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5396D-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5396D-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5396D-A-GMR?

All SI5396D-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5396D-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5396D-A-GMR part is unused and in its original packaging.

Return procedure for SI5396D-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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