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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5396J-A-GM

Name: SI5396J-A-GM
Brand: Skyworks Solutions Inc.
SKU: SI5396J-A-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5396J-A-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5396J-A-GM.pdf

Description:: DUAL PLL JITTER ATTENUATOR WITH

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Product details

Overview

SI5396J-A-GM from Skyworks Solutions is a dual-DSPLL jitter attenuator with integrated crystal reference, 4 differential or LVCMOS inputs, 4 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and ultra-low 95 fs RMS phase jitter. It operates across –40 to +85 °C and supports hitless input switching for telecom timing in Synchronous Ethernet line cards.

For engineers reviewing the SI5396J-A-GM datasheet, SI5396J-A-GM pinout, SI5396J-A-GM application, or SI5396J-A-GM equivalent, key selection criteria include integrated reference elimination of external XTAL layout, per-DSPLL programmable loop bandwidth (0.1 Hz–4 kHz), and independent frequency-on-the-fly reconfiguration without output disruption.

Technical Context

The SI5396J-A-GM implements two independent fourth-generation DSPLLs, each capable of locking to any of four inputs and driving any of four outputs via flexible crosspoint routing. Each DSPLL supports free-run, locked, holdover, and automatic input-switching modes with status monitoring (LOS/OOF/LOL).

It uses an integrated crystal resonator (no external XTAL required), enabling board-space reduction and immunity to acoustic noise during thermal ramping. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent 1.8/2.5/3.3 V output supply pins for signal integrity optimization.

Key Specifications

Parameter	Value and Actual Design Meaning
DSPLL Count	2 independent digital synthesizers for multi-domain synchronization
Output Count	4 configurable clock outputs supporting LVDS, LVPECL, LVCMOS, CML, HCSL
Phase Jitter (RMS)	95 fs typical - meets ITU-T G.8262 SyncE Class C and OTN jitter masks
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy and high-speed interfaces
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10G/25G/100G SerDes rates
Loop Bandwidth	0.1 Hz–4 kHz per DSPLL - enables precise jitter filtering for wander-sensitive applications
Reference Type	Integrated crystal oscillator - eliminates external XTAL, capacitors, and layout sensitivity

Pinout & Package

SI5396J-A-GM is housed in a 44-pin LGA package (7 × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are validated per Skyworks UG336 and Si5396 Family Reference Manual.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or single-ended clock inputs	Supports automatic/manual selection; monitored for LOS/OOF
OUT0–OUT3	Programmable output drivers	Configurable voltage (1.8/2.5/3.3 V), format (LVDS/LVPECL/etc.), and amplitude
XA/XB	Integrated crystal terminals	Internal resonator connection - no external components required
SCL/SDA	I²C serial interface	Used for configuration, status readback, and NVM programming
CSB/SCLK/SDIO	SPI serial interface	Alternative programming interface with faster write throughput
RSTb	Hardware reset input	Active-low hard reset - reloads NVM configuration and resets all logic
LOL0/LOL1	Loss-of-lock indicators	Open-drain outputs signaling loss of phase lock per DSPLL

Key Features

Feature	Design Value
Integrated crystal reference	Eliminates external XTAL, load caps, and associated PCB noise coupling paths
Per-DSPLL hitless switching	Prevents phase transients during input switches between frequency-locked sources (e.g., SyncE primary/backup)
Programmable holdover history	Stores up to 120 s of locked-frequency data to compute stable holdover frequency on input failure
Frequency-on-the-fly (FOTF)	Enables real-time output frequency adjustment per DSPLL without disrupting other outputs
Ramped holdover exit	Linearly transitions output frequency from holdover value to new target - avoids glitches in 56G SerDes recovery

Applications

OTN Muxponder Timing	Synchronous Ethernet Line Card
Use Scenario: Timing recovery and distribution in 100G/400G OTN muxponders requiring low-jitter clock synthesis from multiple line-rate references. IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator synchronizing to OTU4 (111.81 Gbps) or client-side 25G Ethernet clocks while cleaning accumulated jitter. Use Value: 95 fs RMS jitter ensures compliance with ITU-T G.709.1 mask and enables <1e-15 BER in coherent optical receivers.	Use Scenario: Primary/backup clock source in carrier-grade Ethernet switches supporting ITU-T G.8262 EEC Option 2. IC Role / Device Role / Timing Role: Dual-DSPLL device locking to primary SyncE input and holding over to integrated reference upon failure, with hitless switch to secondary input. Use Value: Integrated reference eliminates XTAL drift dependency in holdover, meeting G.8262 wander limits (<4.6 ppm over 24 h).
Broadcast Video Master Clock	100G Carrier Ethernet Switch
Use Scenario: Generation of SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPSDO or PTP grandmaster. IC Role / Device Role / Timing Role: Jitter attenuator converting PTP-derived 10 MHz reference into low-phase-noise video sampling clocks. Use Value: Sub-100 fs jitter prevents pixel timing errors and color banding in 4K/8K broadcast encoders.	Use Scenario: Clock conditioning for 100G QSFP28 ports in metro aggregation switches handling mixed 10G/25G/100G traffic. IC Role / Device Role / Timing Role: Dual-DSPLL jitter cleaner providing independent 100G NRZ and 25G NRZ clocks from common line-card reference. Use Value: Independent DSPLLs allow separate jitter filtering bandwidths optimized for each SerDes lane's requirements.

OTN Muxponder Timing

Synchronous Ethernet Line Card

Use Scenario: Timing recovery and distribution in 100G/400G OTN muxponders requiring low-jitter clock synthesis from multiple line-rate references.

IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator synchronizing to OTU4 (111.81 Gbps) or client-side 25G Ethernet clocks while cleaning accumulated jitter.

Use Value: 95 fs RMS jitter ensures compliance with ITU-T G.709.1 mask and enables <1e-15 BER in coherent optical receivers.

Use Scenario: Primary/backup clock source in carrier-grade Ethernet switches supporting ITU-T G.8262 EEC Option 2.

IC Role / Device Role / Timing Role: Dual-DSPLL device locking to primary SyncE input and holding over to integrated reference upon failure, with hitless switch to secondary input.

Use Value: Integrated reference eliminates XTAL drift dependency in holdover, meeting G.8262 wander limits (<4.6 ppm over 24 h).

Broadcast Video Master Clock

100G Carrier Ethernet Switch

Use Scenario: Generation of SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPSDO or PTP grandmaster.

IC Role / Device Role / Timing Role: Jitter attenuator converting PTP-derived 10 MHz reference into low-phase-noise video sampling clocks.

Use Value: Sub-100 fs jitter prevents pixel timing errors and color banding in 4K/8K broadcast encoders.

Use Scenario: Clock conditioning for 100G QSFP28 ports in metro aggregation switches handling mixed 10G/25G/100G traffic.

IC Role / Device Role / Timing Role: Dual-DSPLL jitter cleaner providing independent 100G NRZ and 25G NRZ clocks from common line-card reference.

Use Value: Independent DSPLLs allow separate jitter filtering bandwidths optimized for each SerDes lane's requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5346A-D-GM	External crystal reference; 44-QFN package; same pin count but no integrated resonator	Requires external 48–54 MHz XTAL and load capacitors; higher layout sensitivity to acoustic noise	Select when existing design uses external crystal and board space allows added components
SI5396K-A-GM	Same integrated reference and LGA package; reduced max output frequency (350 MHz vs 720 MHz)	Lower max output rate limits use in 720 MHz SerDes (e.g., 56G PAM4); otherwise identical functionality	Select when application requires only ≤350 MHz outputs and cost optimization is prioritized

Compared with SI5346A-D-GM, SI5396J-A-GM reduces BOM count and improves thermal stability by integrating the reference; compared with SI5396K-A-GM, it supports higher-frequency 100G/400G SerDes outputs critical for next-gen optical modules.

Availability

SI5396J-A-GM is available at Aetrix Electronics and suitable for OTN muxponders, Synchronous Ethernet line cards, and broadcast video master clock systems requiring stable component supply across extended product lifecycles.

Supply support for SI5396J-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5396 family delivers high-integration jitter attenuation for telecom and datacom timing applications, with grade J specifically engineered for space-constrained, acoustically sensitive SyncE and OTN platforms using integrated reference architecture.

FAQ

What is the reference architecture used in SI5396J-A-GM?

The SI5396J-A-GM uses an integrated crystal resonator - not an external XTAL or XO - eliminating need for external load capacitors and reducing sensitivity to acoustic noise during temperature ramping. This architecture is confirmed in Skyworks' Si5397/Si5396 Ordering Guide (Table 3) and Final Data Sheet Section 1, where Grade J is explicitly designated "Internal" reference.

Does SI5396J-A-GM support hitless switching between two 25 MHz SyncE inputs?

Yes, SI5396J-A-GM supports hitless switching between frequency-locked inputs including 25 MHz SyncE sources. As stated in the Final Data Sheet Section 1 and Figure 7, hitless switching absorbs phase differences during input transitions, preventing output phase transients - a requirement for ITU-T G.8262-compliant line cards.

What output formats and supply voltages does SI5396J-A-GM support?

SI5396J-A-GM supports LVDS, LVPECL, LVCMOS, CML, and HCSL output formats with programmable amplitude. Each output has dedicated supply pins configurable for 1.8 V, 2.5 V, or 3.3 V operation - verified in Final Data Sheet Section 1 Feature List and Section 3 Ordering Guide package notes.

Can SI5396J-A-GM operate without external configuration after power-up?

Yes, SI5396J-A-GM powers up in a known state using factory-programmed non-volatile OTP memory. Initialization completes automatically, and outputs begin generating clocks per stored configuration - confirmed in Final Data Sheet Section 4.4.1 and Section 1 description of "in-circuit programmable non-volatile memory."

What is the maximum output frequency supported by SI5396J-A-GM?

The SI5396J-A-GM supports differential output frequencies up to 720 MHz and LVCMOS outputs up to 250 MHz, as specified in the Final Data Sheet Section 1 Key Features and Table 3 (Si5396J-A-GM ordering row). This enables direct clocking of 100G/400G SerDes lanes and high-speed FPGA interfaces.

SI5396J-A-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

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PLL:: -

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Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

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SI5396J-A-GM FAQ

1.How can I place an order for SI5396J-A-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5396J-A-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5396J-A-GM reliable?

The price and inventory of SI5396J-A-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5396J-A-GM is usually 5 days.

3.What payment methods are accepted for SI5396J-A-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5396J-A-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5396J-A-GM?

SI5396J-A-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5396J-A-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5396J-A-GM?

For technical support, including SI5396J-A-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5396J-A-GM requirements.

6.How does Aetrix verify that SI5396J-A-GM is sourced from the original manufacturer or authorized distributors?

All SI5396J-A-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5396J-A-GM meets industry standards.

7.What is the process for return or replacement of SI5396J-A-GM?

All SI5396J-A-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5396J-A-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5396J-A-GM part is unused and in its original packaging.

Return procedure for SI5396J-A-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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