Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5397J-A-GM

Name: SI5397J-A-GM
Brand: Skyworks Solutions Inc.
SKU: SI5397J-A-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5397J-A-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5397J-A-GM.pdf

Description:: QUAD PLL JITTER ATTENUATOR WITH

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,360

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5397J-A-GM from Skyworks Solutions is a quad-DSPLL jitter attenuator with integrated crystal reference, 4 differential inputs, 8 LVDS/LVPECL/CML/HCSL/LVCMOS outputs, 95 fs rms phase jitter, and programmable loop bandwidth (0.1 Hz–4 kHz). It serves as a high-precision timing engine in OTN transponders requiring synchronous Ethernet (G.8262) compliance and hitless clock switching.

For engineers reviewing the SI5397J-A-GM datasheet, SI5397J-A-GM pinout, SI5397J-A-GM application, or SI5397J-A-GM equivalent, key selection criteria include integrated reference operation, 8-output configuration, 64-LGA 9×9 mm package, DSPLL independence, and support for gapped clock inputs up to 750 MHz.

Technical Context

The SI5397J-A-GM implements four independent fourth-generation DSPLLs, each capable of locking to any of four differential or LVCMOS inputs (8 kHz–750 MHz) and generating any output frequency (100 Hz–720 MHz) via fractional-N synthesis. Each DSPLL supports configurable loop bandwidth, fastlock acquisition, holdover with 120-second frequency history averaging, and DCO mode with 0.01 ppb step resolution.

It integrates a factory-trimmed MEMS-based reference oscillator (eliminating external crystal), operates from 1.8 V core and 3.3 V analog supplies, and features I²C/SPI programmability with on-chip OTP NVM for power-up configuration. Input clock monitoring includes LOS, OOF, and LOL detection per DSPLL.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (rms)	95 fs - enables 100G/400G SerDes compliance and reduces BER in high-speed interfaces
DSPLL count	4 - supports independent synchronization to multiple time domains (e.g., SyncE + OTN + PTP)
Outputs	8 - configurable as LVDS/LVPECL/CML/HCSL/LVCMOS with independent voltage supply pins (1.8/2.5/3.3 V)
Input range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - accommodates telecom, broadcast, and datacom reference clocks
Output range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers PCIe Gen5, 100G KR4, and 25G Ethernet rates
Loop bandwidth	0.1 Hz–4 kHz per DSPLL - enables precise jitter filtering for wander-sensitive applications like SyncE
Reference type	Integrated MEMS oscillator - eliminates crystal BOM, improves acoustic noise immunity, and reduces PCB area

Pinout & Package

SI5397J-A-GM uses a 64-pin LGA package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5397 Family Reference Manual (Rev. 1.3, Section 5.1) and validated against Figure 1 and Table 5 (Pin Descriptions) of the final datasheet.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential input pairs	Accept LVDS/LVPECL/CML clocks; each routed to any DSPLL via crosspoint matrix
OUT0–OUT7	Differential output pairs	Programmable format (LVDS/LVPECL/CML/HCSL); each driven by independent DSPLL
VDD, VDDA	Power supply rails	VDD = 1.8 V ±5% (core); VDDA = 3.3 V ±5% (analog/PLL); decoupling critical for jitter performance
SCL, SDA	I²C interface	Two-wire serial control; supports hot-plug configuration without reset
SDIO, SCLK	SPI interface	Alternative 4-wire serial programming; compatible with standard SPI masters
RSTb	Hardware reset	Active-low asynchronous reset; initiates full initialization and NVM reload
LOL0–LOL3	Loss-of-lock indicators	Open-drain outputs signaling loss of phase lock per DSPLL; used for system fault reporting
LOS0–LOS3	Loss-of-signal indicators	Per-input status flags; asserted when input amplitude falls below threshold or stops toggling

Key Features

Feature	Design Value
Integrated MEMS reference	Eliminates external crystal, reduces board space by ≥30%, and removes sensitivity to acoustic noise during thermal ramping
Hitless input switching	Prevents output phase transients during clock switchover between frequency-locked sources (e.g., 25 MHz SyncE references)
Gapped clock support	Locks to modulated inputs with up to two missing cycles per eight periods - enables frequency averaging for legacy SONET/SDH interfaces
Programmable holdover	Uses 120-second stored frequency history with user-defined averaging window to minimize phase jump on input failure
Frequency-on-the-fly (FOTF)	Allows real-time reconfiguration of output frequency, loop BW, or LOL thresholds on one DSPLL without disrupting other outputs

Applications

OTN Transponders	Synchronous Ethernet Line Cards
Use Scenario: Timing recovery and distribution in 100G/400G OTN muxponders where multiple client-side rates (e.g., 10.7 Gbps, 25.78 Gbps) must be synchronized to line-side 100G/400G OTU4/OTU4.4. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator - cleans incoming client clocks and generates low-jitter line-rate clocks compliant with ITU-T G.709. Use Value: 95 fs rms jitter ensures <1e-12 BER at 400G DP-QPSK, while quad-DSPLL independence allows simultaneous handling of OTU3, OTU4, and FEC clock domains.	Use Scenario: Clock generation and holdover in carrier-grade Ethernet switches supporting ITU-T G.8262 EEC Option 2 for SyncE distribution. IC Role / Device Role / Timing Role: Primary timing IC - locks to primary BITS input, provides redundant holdover using integrated reference, and distributes 125 MHz/156.25 MHz clocks to PHYs and MACs. Use Value: Integrated reference eliminates crystal drift during temperature cycling, and programmable 0.1 Hz loop BW meets G.8262 wander requirements (<4.6 ppm over 1 s).
Broadcast Video Infrastructure	5G Fronthaul Equipment
Use Scenario: Genlock and frame synchronization across SDI routers, IP video gateways, and SMPTE ST 2110-10/20/30 endpoints operating at 27 MHz, 74.25 MHz, and 148.5 MHz. IC Role / Device Role / Timing Role: Multi-format jitter cleaner - accepts tri-level sync, black burst, and PTP-derived clocks, then delivers phase-aligned LVDS outputs to video processing ASICs. Use Value: Independent DSPLLs enable seamless switching between reference sources without visible video artifacts; 8-output capability supports multi-channel 4K/8K routing.	Use Scenario: Timing recovery in eCPRI-over-fiber fronthaul units where CPRI clock (30.72 MHz) and eCPRI packet timestamps must be reconciled with local 100 MHz system clock. IC Role / Device Role / Timing Role: Dual-domain jitter attenuator - one DSPLL locks to recovered eCPRI timing, another to GPS-disciplined OCXO, enabling deterministic latency compensation. Use Value: Hitless switching between GNSS and network-derived timing avoids packet loss during antenna handover; DCO mode supports fine-grained frequency alignment to compensate for fiber delay variation.

OTN Transponders

Synchronous Ethernet Line Cards

Use Scenario: Timing recovery and distribution in 100G/400G OTN muxponders where multiple client-side rates (e.g., 10.7 Gbps, 25.78 Gbps) must be synchronized to line-side 100G/400G OTU4/OTU4.4.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator - cleans incoming client clocks and generates low-jitter line-rate clocks compliant with ITU-T G.709.

Use Value: 95 fs rms jitter ensures <1e-12 BER at 400G DP-QPSK, while quad-DSPLL independence allows simultaneous handling of OTU3, OTU4, and FEC clock domains.

Use Scenario: Clock generation and holdover in carrier-grade Ethernet switches supporting ITU-T G.8262 EEC Option 2 for SyncE distribution.

IC Role / Device Role / Timing Role: Primary timing IC - locks to primary BITS input, provides redundant holdover using integrated reference, and distributes 125 MHz/156.25 MHz clocks to PHYs and MACs.

Use Value: Integrated reference eliminates crystal drift during temperature cycling, and programmable 0.1 Hz loop BW meets G.8262 wander requirements (<4.6 ppm over 1 s).

Broadcast Video Infrastructure

5G Fronthaul Equipment

Use Scenario: Genlock and frame synchronization across SDI routers, IP video gateways, and SMPTE ST 2110-10/20/30 endpoints operating at 27 MHz, 74.25 MHz, and 148.5 MHz.

IC Role / Device Role / Timing Role: Multi-format jitter cleaner - accepts tri-level sync, black burst, and PTP-derived clocks, then delivers phase-aligned LVDS outputs to video processing ASICs.

Use Value: Independent DSPLLs enable seamless switching between reference sources without visible video artifacts; 8-output capability supports multi-channel 4K/8K routing.

Use Scenario: Timing recovery in eCPRI-over-fiber fronthaul units where CPRI clock (30.72 MHz) and eCPRI packet timestamps must be reconciled with local 100 MHz system clock.

IC Role / Device Role / Timing Role: Dual-domain jitter attenuator - one DSPLL locks to recovered eCPRI timing, another to GPS-disciplined OCXO, enabling deterministic latency compensation.

Use Value: Hitless switching between GNSS and network-derived timing avoids packet loss during antenna handover; DCO mode supports fine-grained frequency alignment to compensate for fiber delay variation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5397K-A-GM	Same 4-DSPLL, 8-output, integrated reference architecture but rated for ≤350 MHz max output frequency (vs. 720 MHz)	Targeted at sub-350 MHz applications (e.g., 10G/25G Ethernet, CPRI), not suitable for 400G KR4 or 720 MHz SerDes	Select SI5397J-A-GM when outputs >350 MHz are required; Si5397K-A-GM offers cost optimization for lower-frequency designs
Si5347-A-GM	Legacy 4-DSPLL jitter attenuator with external crystal requirement, 64-QFN package, and 115 fs rms jitter (vs. 95 fs)	Lacks integrated reference and gapped clock support; requires additional crystal BOM and layout care for jitter performance	Choose SI5397J-A-GM for reduced BOM, better jitter, and enhanced reliability; Si5347-A-GM only if legacy design reuse or QFN preference is mandatory

Compared with Si5397K-A-GM and Si5347-A-GM, the SI5397J-A-GM delivers higher maximum output frequency (720 MHz vs. 350 MHz/720 MHz), superior jitter (95 fs vs. 95 fs/115 fs), and integrated reference - making it optimal for next-gen 400G/800G systems where board space, acoustic noise immunity, and SerDes margin are critical.

Availability

SI5397J-A-GM is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, broadcast video infrastructure, and 5G fronthaul equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5397J-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si5397 family is designed for high-density, multi-domain timing applications in optical transport, carrier Ethernet, and broadcast video - delivering ultra-low jitter, integrated reference, and field-programmable flexibility in a single device.

FAQ

What is the reference architecture used in the SI5397J-A-GM?

The SI5397J-A-GM incorporates an integrated MEMS-based reference oscillator, eliminating the need for an external crystal or XO. This design reduces PCB area, improves resistance to acoustic noise during thermal transients, and enhances system reliability. Unlike grades A/B/C/D which require external crystals, the J-grade's internal reference is factory-trimmed and fully characterized for operation across –40 °C to +85 °C. The SI5397J-A-GM does not support external reference connection - doing so may damage the device.

Does the SI5397J-A-GM support gapped clock inputs, and what are the limits?

Yes, the SI5397J-A-GM supports gapped clock inputs - a feature critical for legacy SONET/SDH and CPRI timing recovery. It locks to inputs with up to two missing cycles per eight periods and minimum frequency of 10 MHz. Gapped clock operation does not trigger LOS, OOF, or LOL monitors, and the resulting output is a clean, non-gapped clock at the average input frequency. This capability is confirmed in Section 4.7.8 of the final datasheet and validated for use in fronthaul and transport applications.

How many independent DSPLLs does the SI5397J-A-GM have, and what is their functional independence?

The SI5397J-A-GM contains four fully independent DSPLLs, each with dedicated input routing (to any of IN0–IN3), output assignment (to any of OUT0–OUT7), loop bandwidth (0.1 Hz–4 kHz), holdover configuration, and status monitoring (LOL, LOS, OOF). They share only the serial interface and power domains. This independence enables concurrent synchronization to disparate timing domains - for example, one DSPLL locking to SyncE, another to PTP, a third to OTN, and a fourth to broadcast video sync - without cross-talk or shared failure modes.

What output formats and voltage supplies are supported by the SI5397J-A-GM?

The SI5397J-A-GM supports five output signal formats: LVDS, LVPECL, CML, HCSL, and LVCMOS, each programmable per output pair. It provides independent output supply pins (VDDOx) configurable for 1.8 V, 2.5 V, or 3.3 V operation - allowing mixed-voltage interface support on a single device. This flexibility enables direct connection to diverse PHYs, FPGAs, and ASICs without level-shifting components. All format and voltage settings are stored in non-volatile memory and applied at power-up.

Is the SI5397J-A-GM pin-compatible with earlier Skyworks jitter attenuators?

The SI5397J-A-GM is drop-in compatible with the Si5347 family per Section 1 of the datasheet, sharing identical 64-LGA 9×9 mm footprint and pinout. However, it is not pin-compatible with Si5396 variants (e.g., Si5396J-A-GM), which use 44-LGA packages. Drop-in compatibility assumes identical power sequencing, I²C/SPI address, and register mapping - verified in AN1155. Users must confirm firmware and ClockBuilder Pro configuration compatibility before substitution.

SI5397J-A-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5397J-A-GM FAQ

1.How can I place an order for SI5397J-A-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5397J-A-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5397J-A-GM reliable?

The price and inventory of SI5397J-A-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5397J-A-GM is usually 5 days.

3.What payment methods are accepted for SI5397J-A-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5397J-A-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5397J-A-GM?

SI5397J-A-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5397J-A-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5397J-A-GM?

For technical support, including SI5397J-A-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5397J-A-GM requirements.

6.How does Aetrix verify that SI5397J-A-GM is sourced from the original manufacturer or authorized distributors?

All SI5397J-A-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5397J-A-GM meets industry standards.

7.What is the process for return or replacement of SI5397J-A-GM?

All SI5397J-A-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5397J-A-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5397J-A-GM part is unused and in its original packaging.

Return procedure for SI5397J-A-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…