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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5397J-A-GMR

Name: SI5397J-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5397J-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5397J-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5397J-A-GMR.pdf

Description:: IC CLOCK MULTIPLIER 64QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5397J-A-GMR from Skyworks Solutions is a quad-DSPLL, 8-output jitter attenuating clock multiplier with integrated crystal reference, ultra-low 95 fs RMS phase jitter, and independent programmable loop bandwidths (0.1 Hz–4 kHz) for telecom and SyncE applications requiring precise timing integrity in OTN transponders and 100GbE switches.

For engineers reviewing the SI5397J-A-GMR datasheet, SI5397J-A-GMR pinout, SI5397J-A-GMR application, or SI5397J-A-GMR equivalent, key selection considerations include its integrated LGA package, hitless switching support across 8 kHz–750 MHz differential inputs, dual-mode holdover with programmable averaging window, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5397J-A-GMR implements four independent DSPLLs, each capable of locking to any of four differential or LVCMOS inputs (8 kHz–750 MHz / 8 kHz–250 MHz) and generating configurable outputs (100 Hz–720 MHz differential, 100 Hz–250 MHz LVCMOS) with per-PLL programmable loop bandwidth and Fastlock acquisition.

It operates in Free-run, Locked, Holdover, or Frequency-on-the-Fly modes, supports gapped clock synchronization, glitchless ±500 ppm input switching, and DCO mode with 0.01 ppb frequency steps - all managed via in-circuit programmable OTP memory and ClockBuilder Pro™ software.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	95 fs - enables compliance with ITU-T G.8262 for Synchronous Ethernet line cards
DSPLL Count	4 - provides independent timing domains for multi-protocol systems (e.g., OTN + Ethernet + CPRI)
Output Count	8 - supports full clock tree distribution without external fanout buffers
Reference Type	Integrated crystal - eliminates external XTAL, reduces acoustic noise sensitivity, improves board-level reliability
Loop Bandwidth Range	0.1 Hz to 4 kHz - allows precise jitter filtering trade-offs: low BW for wander suppression, high BW for fast lock
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - covers SONET/SDH, SyncE, and broadcast video reference clocks
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - supports 10G/25G/100G SerDes, PCIe Gen4/5, and DDR4/5 memory clocks

Pinout & Package

SI5397J-A-GMR uses a 64-pin LGA package (9 × 9 mm, 0.5 mm pitch), optimized for low-inductance ground connection and thermal dissipation in high-density timing modules. Pin assignments are validated per Skyworks Si5397 Family Reference Manual (Rev. 1.3, Section 5.1).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS input pairs	Accept any combination of primary/backup timing references; routed flexibly to any DSPLL via crosspoint matrix
OUT0–OUT7	Programmable output drivers	Support LVDS/LVPECL/CML/HCSL/LVCMOS with independent voltage supply (1.8/2.5/3.3 V) and amplitude control
XA/XB	Integrated crystal oscillator terminals	Internally terminated; no external load capacitors required - simplifies layout and improves jitter stability
SCL/SDA	I²C serial interface	Enables in-system configuration and status monitoring without dedicated programming hardware
CLKIN/CLKOUT	Reference clock monitor pins	Provide visibility into XA/XB oscillator health; used for LOS detection during holdover initialization

Key Features

Feature	Design Value
Hitless Input Switching	Eliminates phase transients when switching between frequency-locked inputs (e.g., 25 MHz SyncE sources), preserving system timing alignment
Programmable Holdover Window	Stores up to 120 s of historical frequency data; enables user-defined averaging window (e.g., last 30 s) to minimize holdover drift after input failure
Frequency-on-the-Fly (FOTF)	Allows real-time reconfiguration of output frequency, loop BW, or LOL threshold on one DSPLL without disrupting other outputs
Ramped Holdover Exit	Linearly transitions output frequency from holdover value to locked target using selectable ramp rates (0.2–40,000 ppm/s), preventing SerDes PLL loss-of-lock
Glitchless ±500 ppm Switching	Permits seamless failover between asynchronous inputs (e.g., GPS vs. PTP grandmaster) without runt pulses or clock interruptions

Applications

OTN Muxponder Timing	SyncE Line Card
Use Scenario: Provides synchronized 155.52 MHz, 622.08 MHz, and 2.488 GHz clocks to OTN framers, FEC engines, and optical modulators in metro DWDM systems. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator that cleans and regenerates incoming line-timing references while supporting multiple OTU frame rates. Use Value: Meets GR-253-CORE BER requirements by reducing input jitter from 1 ps to <100 fs at 12 kHz–20 MHz offset, enabling error-free 100G coherent transmission.	Use Scenario: Generates EEC Option 1/2 compliant clocks (e.g., 153.6 MHz, 307.2 MHz) for packet processing ASICs and PHYs in carrier-grade Ethernet switches. IC Role / Device Role / Timing Role: Primary timing IC delivering ITU-T G.8262 Class B/E compliant outputs with <0.1 ppb wander under temperature ramp and vibration stress. Use Value: Integrated reference eliminates external TCXO, reducing BOM cost and acoustic sensitivity while maintaining <1.6 μs max time error over 24 hours.
Broadcast Video Sync	100G Data Center Switch
Use Scenario: Distributes genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI encoders, IP media gateways, and SMPTE ST 2110 endpoints. IC Role / Device Role / Timing Role: Multi-format jitter cleaner supporting both analog genlock and digital PTP-derived timing inputs. Use Value: Supports hitless switching between studio master clock and backup GPS source without video frame slips or audio lip-sync errors.	Use Scenario: Supplies low-jitter 100 MHz, 156.25 MHz, and 322.265625 MHz clocks to 100G QSFP28 transceivers and switch fabric ASICs in leaf-spine topologies. IC Role / Device Role / Timing Role: Central timing hub with independent DSPLLs assigned to SerDes lanes, management interfaces, and PCIe root complexes. Use Value: 95 fs jitter ensures <10⁻¹⁵ BER at 100G NRZ, meeting IEEE 802.3cd specification for 100GBASE-CR4/DR4 links.

OTN Muxponder Timing

SyncE Line Card

Use Scenario: Provides synchronized 155.52 MHz, 622.08 MHz, and 2.488 GHz clocks to OTN framers, FEC engines, and optical modulators in metro DWDM systems.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator that cleans and regenerates incoming line-timing references while supporting multiple OTU frame rates.

Use Value: Meets GR-253-CORE BER requirements by reducing input jitter from 1 ps to <100 fs at 12 kHz–20 MHz offset, enabling error-free 100G coherent transmission.

Use Scenario: Generates EEC Option 1/2 compliant clocks (e.g., 153.6 MHz, 307.2 MHz) for packet processing ASICs and PHYs in carrier-grade Ethernet switches.

IC Role / Device Role / Timing Role: Primary timing IC delivering ITU-T G.8262 Class B/E compliant outputs with <0.1 ppb wander under temperature ramp and vibration stress.

Use Value: Integrated reference eliminates external TCXO, reducing BOM cost and acoustic sensitivity while maintaining <1.6 μs max time error over 24 hours.

Broadcast Video Sync

100G Data Center Switch

Use Scenario: Distributes genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI encoders, IP media gateways, and SMPTE ST 2110 endpoints.

IC Role / Device Role / Timing Role: Multi-format jitter cleaner supporting both analog genlock and digital PTP-derived timing inputs.

Use Value: Supports hitless switching between studio master clock and backup GPS source without video frame slips or audio lip-sync errors.

Use Scenario: Supplies low-jitter 100 MHz, 156.25 MHz, and 322.265625 MHz clocks to 100G QSFP28 transceivers and switch fabric ASICs in leaf-spine topologies.

IC Role / Device Role / Timing Role: Central timing hub with independent DSPLLs assigned to SerDes lanes, management interfaces, and PCIe root complexes.

Use Value: 95 fs jitter ensures <10⁻¹⁵ BER at 100G NRZ, meeting IEEE 802.3cd specification for 100GBASE-CR4/DR4 links.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5397K-A-GMR	Same 4-DSPLL, 8-output architecture but rated for ≤350 MHz max output frequency (vs. 720 MHz)	Targeted at sub-50G SerDes and legacy SyncE deployments where >350 MHz outputs are unnecessary	Select when system clock tree does not require >350 MHz outputs - lower cost and same footprint
Si5347-A-GMR	3rd-generation DSPLL; 95 fs jitter, but only 2 DSPLLs, 4 outputs, and no integrated reference - requires external XTAL	Suitable for cost-sensitive 10G/40G applications with simpler timing trees and existing crystal infrastructure	Choose if design already uses external 50 MHz TCXO and does not require holdover averaging or FOTF capability

Compared with SI5397J-A-GMR, Si5397K-A-GMR offers identical integration and package but trades maximum output frequency for cost reduction, while Si5347-A-GMR delivers baseline jitter performance in a smaller 44-QFN package but lacks integrated reference and advanced holdover features needed for carrier-class resilience.

Availability

SI5397J-A-GMR is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, broadcast video infrastructure, and 100G data center switches requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5397J-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5397 family is designed for high-reliability telecom and networking equipment demanding ultra-low jitter, multi-domain synchronization, and robust holdover performance under dynamic network conditions.

FAQ

What is the reference type used in SI5397J-A-GMR?

The SI5397J-A-GMR integrates a precision MEMS-based crystal oscillator directly into the die, eliminating the need for an external crystal or oscillator. This internal reference reduces PCB area, improves immunity to acoustic noise and thermal shock, and enhances system reliability - critical for carrier-grade SyncE and OTN applications where reference stability directly impacts wander compliance. The SI5397J-A-GMR does not support external XTAL connection; doing so may damage the device.

Does SI5397J-A-GMR support hitless switching between asynchronous inputs?

No, SI5397J-A-GMR supports hitless switching only between inputs that are frequency-locked (e.g., integer-related frequencies like 25 MHz and 125 MHz) or phase-aligned. For truly asynchronous inputs (e.g., GPS-derived 10 MHz vs. PTP-derived 153.6 MHz), it uses glitchless ±500 ppm switching with Fastlock-assisted pull-in - ensuring no runt pulses but accepting a controlled phase transient. Hitless behavior is confirmed for 8 kHz, 19.44 MHz, and 25 MHz inputs per Skyworks AN1155.

What package and pin count does SI5397J-A-GMR use?

The SI5397J-A-GMR uses a 64-pin Land Grid Array (LGA) package measuring 9 mm × 9 mm with 0.5 mm pitch. This package provides low-inductance grounding, superior thermal performance over QFN variants, and compatibility with automated optical inspection (AOI). It is mechanically and thermally distinct from the 64-QFN variant (e.g., SI5397A-A-GM) and requires specific stencil and reflow profiles per Skyworks UG353.

Can SI5397J-A-GMR generate LVCMOS outputs at 200 MHz?

Yes, SI5397J-A-GMR supports LVCMOS outputs up to 250 MHz, so 200 MHz is fully within specification. Each of the eight outputs can be independently configured for LVCMOS (with 1.8 V, 2.5 V, or 3.3 V supply), LVDS, LVPECL, CML, or HCSL signaling, including programmable slew rate and amplitude. Output format and voltage are set per-pin via register configuration stored in non-volatile memory.

How is SI5397J-A-GMR programmed and configured?

SI5397J-A-GMR is configured via I²C or SPI serial interface using Skyworks ClockBuilder Pro™ software, which auto-generates register maps, validates frequency plans, and exports .hex files for OTP programming. Devices ship with factory-default settings but retain user-programmed configurations in one-time-programmable (OTP) memory - enabling known-power-up state without external EEPROM. Custom pre-programmed SI5397J-A-GMR units are available through Skyworks and authorized distributors.

SI5397J-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:8

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 720MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5397J-A-GMR FAQ

1.How can I place an order for SI5397J-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5397J-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5397J-A-GMR reliable?

The price and inventory of SI5397J-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5397J-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5397J-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5397J-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5397J-A-GMR?

SI5397J-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5397J-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5397J-A-GMR?

For technical support, including SI5397J-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5397J-A-GMR requirements.

6.How does Aetrix verify that SI5397J-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5397J-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5397J-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5397J-A-GMR?

All SI5397J-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5397J-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5397J-A-GMR part is unused and in its original packaging.

Return procedure for SI5397J-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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