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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5397K-A-GM

Name: SI5397K-A-GM
Brand: Skyworks Solutions Inc.
SKU: SI5397K-A-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5397K-A-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5397K-A-GM.pdf

Description:: QUAD PLL JITTER ATTENUATOR WITH

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Product details

Overview

SI5397K-A-GM from Skyworks Solutions is a 4-DSPLL, 4-input/8-output jitter-attenuating clock multiplier with integrated crystal reference, delivering 95 fs rms phase jitter, 0.1 Hz–4 kHz programmable loop bandwidth per DSPLL, and support for differential (up to 350 MHz) and LVCMOS (up to 250 MHz) outputs. It serves as a timing engine in Synchronous Ethernet line cards and OTN transponders requiring hitless switching and holdover stability.

For engineers reviewing the SI5397K-A-GM datasheet, SI5397K-A-GM pinout, SI5397K-A-GM application, or SI5397K-A-GM equivalent, key selection considerations include its integrated reference architecture, 64-LGA 9×9 mm package, dual-mode operation (locked/holdover), and compatibility with ClockBuilder Pro™ configuration - critical for telecom PLL design and multi-domain synchronization.

Technical Context

The SI5397K-A-GM implements four independent DSPLLs, each configurable to any of four inputs (IN0–IN3) via flexible crosspoint routing, enabling simultaneous synchronization to multiple time domains. Each DSPLL supports free-run, locked, and holdover modes with programmable fastlock bandwidth (100 Hz–4 kHz) and full frequency-on-the-fly reconfiguration.

It uses an integrated crystal reference (grade K), eliminating external XTAL components and reducing acoustic noise sensitivity during thermal ramping. Output clocks are fully programmable across LVDS, LVPECL, LVCMOS, CML, and HCSL formats with independent supply pins (1.8 V/2.5 V/3.3 V) and signal amplitude control.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (rms)	95 fs - enables compliance with ITU-T G.8262 SyncE Class C and 100G/400G Ethernet jitter budgets
DSPLL count	4 - provides independent timing paths for up to four distinct system domains (e.g., MAC, PHY, SerDes, management)
Input frequency range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy T1/E1, SyncE, and high-speed SerDes reference inputs
Output frequency range	Differential: 100 Hz–350 MHz; LVCMOS: 100 Hz–250 MHz - covers 10G/25G/100G Ethernet rates and broadcast video pixel clocks
Loop bandwidth	0.1 Hz–4 kHz per DSPLL - allows precise jitter filtering trade-offs: low BW for wander suppression, high BW for fast lock
Reference type	Integrated crystal - removes external XTAL, capacitors, and layout sensitivity; improves board-level reliability and EMI immunity
Package	64-LGA, 9 × 9 mm - surface-mount compatible with standard reflow profiles; no exposed pad required

Pinout & Package

SI5397K-A-GM is housed in a 64-pin Land Grid Array (LGA) package, 9 mm × 9 mm, 0.5 mm pitch, with bottom-side thermal pad (non-electrical). Pin functions are defined per Skyworks Si5397 Family Reference Manual (Rev. 1.3, Section 5.1).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential input pairs	Accept LVDS/LVPECL/CML clocks; support gapped clock locking and automatic LOS/OOF monitoring
OUT0–OUT7	Differential output pairs	Programmable format (LVDS/LVPECL/HCSL/CML); independent voltage supply (VDDOx) per bank
XA/XB	Integrated crystal terminals	Internally connected to on-die resonator; no external components required; not user-accessible
SCL/SDA	I²C interface	2-wire serial control; supports hot-plug configuration and status readback without reset
CSB/SCLK/SDIO	SPI interface	4-wire alternative; enables faster programming and multi-device daisy-chaining
RSTb	Hardware reset	Active-low asynchronous reset; triggers full NVM reload and DSPLL reinitialization

Key Features

Feature	Design Value
Integrated crystal reference	Eliminates external XTAL, load caps, and associated PCB area; reduces acoustic noise coupling during temperature transients
Per-DSPLL hitless switching	Prevents phase transients during input clock switches between frequency-locked sources (e.g., 25 MHz SyncE primary/backup)
Programmable holdover window	Stores 120 s of historical frequency data; calculates final holdover frequency from user-defined averaging window (1–120 s)
Ramped holdover exit	Linearly transitions output frequency from holdover value to target lock frequency using selectable ramp rates (0.2–40,000 ppm/s)
Frequency-on-the-fly (FOTF)	Reconfigures output frequency, loop BW, or LOL threshold on one DSPLL without disrupting other outputs or requiring full device reset

Applications

OTN Transponder Timing	Synchronous Ethernet Line Card
Use Scenario: Provides low-jitter clock synthesis for 100G/400G OTN muxponders where multiple SerDes lanes require independent, phase-aligned clocks derived from diverse network references. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator - accepts OC-192/STM-64 or PTP grandmaster inputs and generates clean 156.25 MHz, 311.04 MHz, and 622.08 MHz SerDes reference clocks. Use Value: 95 fs rms jitter ensures BER <1e-12 at 112 Gbps PAM4; integrated reference eliminates XTAL placement sensitivity near high-speed traces.	Use Scenario: Generates ITU-T G.8262-compliant clocks for carrier-grade Ethernet switches handling mixed 10G/25G/100G traffic with strict wander and jitter limits. IC Role / Device Role / Timing Role: Dual-domain PLL - one DSPLL locks to primary SyncE input (e.g., 153.6 MHz), second maintains holdover using averaged history during input failure. Use Value: Programmable 0.1 Hz loop bandwidth suppresses wander; ramped holdover exit prevents packet loss during recovery from reference outage.
Broadcast Video Distribution	5G Fronthaul Baseband Unit
Use Scenario: Distributes synchronized pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) across SMPTE ST 2110 IP video routers with sub-sample phase alignment. IC Role / Device Role / Timing Role: Multi-format jitter cleaner - accepts AES67 PTP or SDI tri-level sync and delivers LVCMOS/LVDS clocks with <1 ns inter-output skew. Use Value: Independent DSPLLs enable separate jitter filtering for video vs. audio domains; LVCMOS outputs drive FPGA I/O banks directly without level-shifting.	Use Scenario: Supplies phase-coherent clocks to massive MIMO RFICs and eCPRI fronthaul interfaces in 5G base stations operating under variable backhaul reference conditions. IC Role / Device Role / Timing Role: Adaptive timing manager - switches between GPS-disciplined OCXO, fronthaul CPRI clock, and local holdover without disrupting beamforming DSP timing. Use Value: Hitless switching preserves symbol alignment across antenna arrays; DCO mode enables fine frequency tuning for eCPRI latency compensation.

OTN Transponder Timing

Synchronous Ethernet Line Card

Use Scenario: Provides low-jitter clock synthesis for 100G/400G OTN muxponders where multiple SerDes lanes require independent, phase-aligned clocks derived from diverse network references.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator - accepts OC-192/STM-64 or PTP grandmaster inputs and generates clean 156.25 MHz, 311.04 MHz, and 622.08 MHz SerDes reference clocks.

Use Value: 95 fs rms jitter ensures BER <1e-12 at 112 Gbps PAM4; integrated reference eliminates XTAL placement sensitivity near high-speed traces.

Use Scenario: Generates ITU-T G.8262-compliant clocks for carrier-grade Ethernet switches handling mixed 10G/25G/100G traffic with strict wander and jitter limits.

IC Role / Device Role / Timing Role: Dual-domain PLL - one DSPLL locks to primary SyncE input (e.g., 153.6 MHz), second maintains holdover using averaged history during input failure.

Use Value: Programmable 0.1 Hz loop bandwidth suppresses wander; ramped holdover exit prevents packet loss during recovery from reference outage.

Broadcast Video Distribution

5G Fronthaul Baseband Unit

Use Scenario: Distributes synchronized pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) across SMPTE ST 2110 IP video routers with sub-sample phase alignment.

IC Role / Device Role / Timing Role: Multi-format jitter cleaner - accepts AES67 PTP or SDI tri-level sync and delivers LVCMOS/LVDS clocks with <1 ns inter-output skew.

Use Value: Independent DSPLLs enable separate jitter filtering for video vs. audio domains; LVCMOS outputs drive FPGA I/O banks directly without level-shifting.

Use Scenario: Supplies phase-coherent clocks to massive MIMO RFICs and eCPRI fronthaul interfaces in 5G base stations operating under variable backhaul reference conditions.

IC Role / Device Role / Timing Role: Adaptive timing manager - switches between GPS-disciplined OCXO, fronthaul CPRI clock, and local holdover without disrupting beamforming DSP timing.

Use Value: Hitless switching preserves symbol alignment across antenna arrays; DCO mode enables fine frequency tuning for eCPRI latency compensation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5397J-A-GM	Same 4-DSPLL, 8-output, 64-LGA architecture but rated for 0.0001–720 MHz output range (vs. 350 MHz max for SI5397K-A-GM)	Required for designs needing >350 MHz outputs (e.g., 622.08 MHz OTN, 720 MHz SerDes)	Select SI5397K-A-GM when maximum output frequency ≤350 MHz to optimize cost and power; choose J-grade for wider frequency coverage.
Si5396K-A-GM	2-DSPLL, 4-output variant in 44-LGA package; identical integrated reference and jitter performance (95 fs), but half the DSPLL count and output count	Suitable for simpler timing architectures (e.g., single-domain 25G switch, compact fronthaul unit) where 4 outputs suffice	Choose SI5397K-A-GM when ≥4 independent timing domains or ≥8 outputs are required; Si5396K-A-GM reduces footprint and BOM for lower-complexity systems.

Compared with SI5397J-A-GM, SI5397K-A-GM trades maximum output frequency (350 MHz vs. 720 MHz) for optimized cost and power in mid-band applications; versus Si5396K-A-GM, it doubles DSPLL count and output capability while retaining identical jitter, holdover, and integration benefits - making it the preferred choice for multi-domain telecom infrastructure.

Availability

SI5397K-A-GM is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, broadcast video routers, and 5G fronthaul units requiring stable component supply across extended product lifecycles.

Supply support for SI5397K-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5397 family targets high-reliability telecom and datacom timing applications, delivering ultra-low jitter, multi-DSPLL flexibility, and integrated reference architecture to simplify SyncE, OTN, and 5G infrastructure clock trees.

FAQ

What is the maximum differential output frequency supported by the SI5397K-A-GM?

The SI5397K-A-GM supports differential output frequencies up to 350 MHz, as specified in Table 3 of the Skyworks Si5397/Si5396 Ordering Guide for J/K/L/M grades. This limit applies to LVDS, LVPECL, and HCSL output formats. For applications requiring higher frequencies (e.g., 622.08 MHz), the SI5397J-A-GM variant must be selected.

Does the SI5397K-A-GM require external crystals or load capacitors?

No. The SI5397K-A-GM is a grade-K device with an integrated crystal reference, meaning the resonator is embedded within the die. No external XTAL, load capacitors, or supporting circuitry is needed - simplifying layout, improving reliability, and reducing acoustic noise susceptibility during thermal transients.

How does holdover operation work on the SI5397K-A-GM?

The SI5397K-A-GM stores up to 120 seconds of historical input frequency data while locked. Upon input failure, it calculates a final holdover frequency from a programmable window (1–120 s) of that history. The output then ramps linearly to this frequency using user-selectable rates (0.2–40,000 ppm/s), minimizing phase disturbance during recovery.

Can the SI5397K-A-GM perform hitless switching between two 25 MHz SyncE inputs?

Yes. The SI5397K-A-GM supports hitless switching between frequency-locked inputs such as two 25 MHz SyncE sources. When enabled, the DSPLL absorbs phase differences during the switch, preventing output phase transients - critical for maintaining packet integrity in carrier Ethernet applications.

What serial interfaces does the SI5397K-A-GM support for configuration?

The SI5397K-A-GM supports both I²C (SCL/SDA) and SPI (CSB/SCLK/SDIO) interfaces for register programming and status monitoring. I²C enables simple 2-wire configuration and hot-plug updates; SPI offers faster write speeds and daisy-chain capability for multi-device timing systems.

SI5397K-A-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5397K-A-GM FAQ

1.How can I place an order for SI5397K-A-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5397K-A-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5397K-A-GM reliable?

The price and inventory of SI5397K-A-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5397K-A-GM is usually 5 days.

3.What payment methods are accepted for SI5397K-A-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5397K-A-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5397K-A-GM?

SI5397K-A-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5397K-A-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5397K-A-GM?

For technical support, including SI5397K-A-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5397K-A-GM requirements.

6.How does Aetrix verify that SI5397K-A-GM is sourced from the original manufacturer or authorized distributors?

All SI5397K-A-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5397K-A-GM meets industry standards.

7.What is the process for return or replacement of SI5397K-A-GM?

All SI5397K-A-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5397K-A-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5397K-A-GM part is unused and in its original packaging.

Return procedure for SI5397K-A-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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