Skyworks Solutions Inc. SI5397L-A-GM

Overview

SI5397L-A-GM from Skyworks Solutions is a quad-DSPLL jitter attenuator with integrated crystal reference, 4 inputs, 4 differential/LVCMOS outputs, 95 fs rms phase jitter, and programmable loop bandwidth (0.1 Hz–4 kHz). It serves as a high-precision timing engine in Synchronous Ethernet line cards requiring holdover stability and hitless clock switching.

For engineers reviewing the SI5397L-A-GM datasheet, SI5397L-A-GM pinout, SI5397L-A-GM application, or SI5397L-A-GM equivalent, key selection criteria include integrated reference operation, 4-PLL independent frequency synthesis, 720 MHz max differential output, LGA-64 9×9 mm package, and I²C/SPI programmability with OTP NVM.

Technical Context

The SI5397L-A-GM implements four independent digital-synthesis PLLs (DSPLLs), each capable of locking to any of four input clocks (8 kHz–750 MHz differential) and generating any output frequency (100 Hz–720 MHz differential) via fractional-N synthesis. Its integrated crystal eliminates external XTAL components and reduces acoustic noise sensitivity during thermal ramping.

Each DSPLL supports automatic hitless switching between frequency-locked inputs, programmable holdover using 120-second frequency history averaging, and Frequency-on-the-Fly (FOTF) reconfiguration without disrupting other PLLs. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent output voltage rails (1.8/2.5/3.3 V).

Key Specifications

Pinout & Package

SI5397L-A-GM uses a 64-pin Land Grid Array (LGA) package, 9 mm × 9 mm, 0.5 mm pitch, with exposed thermal pad. Pin functions are defined per Skyworks Si5397 Family Reference Manual (Rev. 1.3, Section 5.1) and validated against Figure 1 and Table 5 (Pin Descriptions) of the February 2025 datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with Si5397J-A-GM, SI5397L-A-GM enables higher-speed SerDes clocking up to 720 MHz; compared with Si5347-A-GM, it delivers 30 fs lower jitter, eliminates XTAL BOM, and adds programmable holdover - making it the preferred choice for new SyncE, OTN, and 100G+ designs.

Availability

SI5397L-A-GM is available at Aetrix Electronics and suitable for Synchronous Ethernet line cards, OTN muxponders, broadcast video infrastructure, and 100G carrier Ethernet switches requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5397L-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.

The Si5397 family is engineered for high-reliability telecom and datacom timing applications demanding ultra-low jitter, multi-domain synchronization, and robust holdover - specifically targeting SyncE, OTN, and 100G+ Ethernet infrastructure.

FAQ

What is the reference architecture used in SI5397L-A-GM?

The SI5397L-A-GM integrates a factory-trimmed MEMS-based crystal resonator directly into the die, eliminating the need for an external crystal or oscillator. This Grade L device uses internal loading capacitance and operates at 48–54 MHz, providing improved immunity to acoustic noise and thermal drift versus discrete XTAL solutions. The integrated reference powers all four DSPLLs and enables stable freerun and holdover operation without external components.

Does SI5397L-A-GM support hitless switching between two 25 MHz SyncE inputs?

Yes, SI5397L-A-GM supports hitless switching between two 25 MHz inputs when they are frequency-locked (0 ppm offset) or integer-related. The DSPLL absorbs phase differences during the switch, preventing output phase transients that could disrupt 100G SerDes lock. Hitless switching is enabled per DSPLL via register control and is validated down to 8 kHz, though optimal performance occurs at ≥19.44 MHz per AN1155 and UG353 test reports.

What output formats and voltage levels does SI5397L-A-GM support?

SI5397L-A-GM supports LVDS, LVPECL, CML, HCSL, and LVCMOS output formats across its four differential outputs (OUT0–OUT3). Each output pair has an independent supply pin (VDDOx) configurable for 1.8 V, 2.5 V, or 3.3 V operation, enabling direct interfacing with diverse SerDes, FPGA, and ASIC clock inputs without level-shifting circuitry. Format and amplitude are register-programmable per output.

How is holdover performance configured in SI5397L-A-GM?

Holdover in SI5397L-A-GM is configured via two programmable parameters: historical window size (1–120 seconds) and delay offset (to exclude corrupted pre-failure data). The DSPLL computes an averaged holdover frequency from this window, minimizing phase disturbance during reference loss. Configuration is done through ClockBuilder Pro or direct register writes; default settings per UG353 yield <±0.1 ppm accuracy over 24 hours at +25°C with integrated reference.

Is SI5397L-A-GM pin-compatible with earlier Si5347 devices?

No, SI5397L-A-GM is not pin-compatible with Si5347 devices. While Skyworks states "drop-in compatible" in marketing context, SI5397L-A-GM uses a 64-LGA package with different pin mapping (e.g., XA/XB dedicated to integrated crystal, no external XTAL pins), whereas Si5347-A-GM uses 64-QFN with XA/XB routed for external crystal. PCB redesign is required; migration requires layout revision and updated firmware configuration via ClockBuilder Pro.