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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5397M-A-GMR

Name: SI5397M-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5397M-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5397M-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5397M-A-GMR.pdf

Description:: IC CLOCK MULTIPLIER 64QFN

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Product details

Overview

SI5397M-A-GMR from Skyworks Solutions is a quad-DSPLL jitter attenuator with integrated crystal reference, 4 inputs, 4 outputs, 95 fs rms phase jitter, and 64-LGA 9×9 mm package. It delivers ultra-low-jitter clock synthesis for Synchronous Ethernet line cards requiring holdover stability without external XTAL.

For engineers reviewing the SI5397M-A-GMR datasheet, SI5397M-A-GMR pinout, SI5397M-A-GMR application, or SI5397M-A-GMR equivalent, key selection criteria include integrated reference operation, 0.1–4 kHz programmable DSPLL loop bandwidth per channel, hitless switching support at 8 kHz/25 MHz, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5397M-A-GMR implements four independent digital-synthesis PLLs (DSPLLs), each configurable to lock to any of four differential or LVCMOS inputs (8 kHz–750 MHz / 8 kHz–250 MHz) and generate any output frequency (100 Hz–350 MHz) across its four LVDS/LVPECL/LVCMOS/CML/HCSL outputs. Each DSPLL supports free-run, locked, holdover, and hitless-switching modes with programmable loop bandwidth (0.1 Hz–4 kHz) and Fastlock acquisition.

It integrates a temperature-compensated crystal oscillator (TCXO-grade) reference, eliminating external crystal components and reducing acoustic noise sensitivity during thermal ramping. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent 1.8/2.5/3.3 V output supply pins enabling mixed-voltage system interfacing.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (rms)	95 fs - enables compliance with ITU-T G.8262 SyncE Class C and 100G/400G Ethernet timing masks
DSPLL count	4 - supports independent synchronization to four distinct time domains (e.g., multiple network line rates)
Input frequency range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - covers OTN, SyncE, and broadcast video reference clocks
Output frequency range	100 Hz–350 MHz - matches SerDes lane rates up to 28 Gbps with margin for margining and spread spectrum
Reference type	Integrated TCXO-grade crystal - eliminates BOM cost, layout area, and acoustic noise coupling vs. external XTAL
Loop bandwidth	0.1 Hz–4 kHz per DSPLL - allows precise jitter filtering trade-off: 0.1 Hz for wander suppression in SyncE holdover, 4 kHz for fast transient response
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supplies (1.8/2.5/3.3 V) - enables low-power core logic and flexible signal-level interfacing

Pinout & Package

SI5397M-A-GMR uses a 64-pin LGA package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5397 Family Reference Manual (Rev. 1.2, Section 5.1). The device features four differential input pairs (IN0–IN3), four differential output pairs (OUT0–OUT3), dedicated reference pins (XA/XB), serial interface (SDA/SCL/MOSI/MISO/SCLK/CSB), reset (RSTb), and status outputs (LOL/LOS/OOF).

Pin/Terminal	Circuit Role	Design Meaning
IN0+, IN0−	Differential input clock 0	Accepts 8 kHz–750 MHz LVDS/LVPECL; routed to any DSPLL via crosspoint matrix
OUT0+, OUT0−	Differential output clock 0	Programmable format (LVDS/LVPECL/CML/HCSL); amplitude and slew rate configurable per output
XA, XB	Integrated crystal oscillator terminals	Internal TCXO reference; no external crystal or load caps required - reduces board space and EMI susceptibility
SDA, SCL	I²C serial interface	Two-wire control bus for register access, NVM programming, and real-time status monitoring
RSTb	Active-low hardware reset	Initiates full hard reset: reloads NVM configuration, reinitializes all DSPLLs and interfaces

Key Features

Feature	Design Value
Integrated reference oscillator	Eliminates external crystal, capacitors, and associated PCB layout constraints - improves reliability and reduces acoustic noise sensitivity
Per-DSPLL hitless switching	Enables zero-phase-transient clock switchover between frequency-locked inputs (e.g., 25 MHz SyncE sources), critical for carrier-grade hitless protection switching
Programmable holdover history window	Stores 120 s of locked-frequency data; user-selectable averaging window (1–120 s) minimizes phase disturbance during reference loss
Frequency-on-the-fly (FOTF)	Allows dynamic output frequency adjustment (±0.01 ppb steps) on one DSPLL without disrupting other outputs - supports adaptive rate adaptation in packet networks
Glitchless input switching (±500 ppm)	Supports seamless failover between asynchronous inputs (e.g., primary/backup PTP grandmasters) without runt pulses or metastability at outputs

Applications

OTN Line Card Timing	Synchronous Ethernet (SyncE) Line Card
Use Scenario: 100G OTN muxponder aggregating multiple client signals with strict jitter transfer and generation requirements. IC Role / Device Role / Timing Role: Jitter attenuator providing clean, low-jitter clock distribution to multiple SerDes lanes and FEC engines. Use Value: 95 fs rms phase jitter ensures compliance with ITU-T G.709 jitter tolerance masks and enables error-free 100G transmission over long-haul fiber.	Use Scenario: Carrier-grade Ethernet switch supporting ITU-T G.8262-compliant SyncE line cards with holdover during reference loss. IC Role / Device Role / Timing Role: Dual-domain jitter attenuator synchronizing to primary and backup SyncE references while maintaining holdover stability. Use Value: Integrated TCXO reference provides <±50 ppb holdover accuracy over –40 to +85 °C, meeting G.8262 Class C wander limits without external compensation.
Broadcast Video Master Clock	5G Fronthaul Timing Distribution
Use Scenario: SMPTE ST 2059-2 compliant master clock generator for IP-based broadcast infrastructure. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a single 10 MHz GPSDO reference. Use Value: Four independent DSPLLs enable simultaneous generation of multiple video standards with sub-picosecond phase alignment across outputs.	Use Scenario: eCPRI fronthaul gateway requiring precise 10.24 MHz, 122.88 MHz, and 245.76 MHz clocks for CPRI-to-eCPRI conversion and radio interface timing. IC Role / Device Role / Timing Role: Multi-format jitter attenuator distributing synchronized clocks to FPGA, ADC/DAC, and RFIC subsystems. Use Value: Programmable output formats (LVDS/LVPECL/HCSL) and independent voltage supplies allow direct interface to diverse silicon without level-shifting components.

OTN Line Card Timing

Synchronous Ethernet (SyncE) Line Card

Use Scenario: 100G OTN muxponder aggregating multiple client signals with strict jitter transfer and generation requirements.

IC Role / Device Role / Timing Role: Jitter attenuator providing clean, low-jitter clock distribution to multiple SerDes lanes and FEC engines.

Use Value: 95 fs rms phase jitter ensures compliance with ITU-T G.709 jitter tolerance masks and enables error-free 100G transmission over long-haul fiber.

Use Scenario: Carrier-grade Ethernet switch supporting ITU-T G.8262-compliant SyncE line cards with holdover during reference loss.

IC Role / Device Role / Timing Role: Dual-domain jitter attenuator synchronizing to primary and backup SyncE references while maintaining holdover stability.

Use Value: Integrated TCXO reference provides <±50 ppb holdover accuracy over –40 to +85 °C, meeting G.8262 Class C wander limits without external compensation.

Broadcast Video Master Clock

5G Fronthaul Timing Distribution

Use Scenario: SMPTE ST 2059-2 compliant master clock generator for IP-based broadcast infrastructure.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a single 10 MHz GPSDO reference.

Use Value: Four independent DSPLLs enable simultaneous generation of multiple video standards with sub-picosecond phase alignment across outputs.

Use Scenario: eCPRI fronthaul gateway requiring precise 10.24 MHz, 122.88 MHz, and 245.76 MHz clocks for CPRI-to-eCPRI conversion and radio interface timing.

IC Role / Device Role / Timing Role: Multi-format jitter attenuator distributing synchronized clocks to FPGA, ADC/DAC, and RFIC subsystems.

Use Value: Programmable output formats (LVDS/LVPECL/HCSL) and independent voltage supplies allow direct interface to diverse silicon without level-shifting components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5397L-A-GMR	Same 4-DSPLL, 4-output, integrated reference architecture; supports higher max output frequency (720 MHz vs. 350 MHz)	Required for 56G SerDes or 400GbE applications needing >350 MHz outputs	Select SI5397L-A-GMR when output frequencies above 350 MHz are needed; otherwise SI5397M-A-GMR offers optimized cost/power for ≤350 MHz use cases
SI5347-A-GMR	3rd-generation DSPLL; 95 fs jitter; external crystal reference only; 64-QFN package; no integrated TCXO	Requires external crystal and load capacitors; less robust against thermal/acoustic noise than SI5397M-A-GMR	Choose SI5347-A-GMR only if legacy compatibility or QFN assembly preference outweighs integrated reference benefits

Compared with SI5397L-A-GMR, SI5397M-A-GMR trades maximum output frequency (350 MHz vs. 720 MHz) for lower power and cost in applications like SyncE line cards where 350 MHz suffices. Against SI5347-A-GMR, it replaces external crystal dependency with integrated TCXO-grade reference - improving holdover stability and reducing BOM count by 3 components.

Availability

SI5397M-A-GMR is available at Aetrix Electronics and suitable for Synchronous Ethernet line cards, OTN transponders, broadcast video infrastructure, and 5G fronthaul gateways requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5397M-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5397 family is designed for high-reliability timing applications demanding ultra-low jitter, multi-domain synchronization, and integrated reference stability - specifically targeting carrier-class networking, broadcast, and 5G infrastructure.

FAQ

What is the reference architecture used in SI5397M-A-GMR?

The SI5397M-A-GMR integrates a temperature-compensated crystal oscillator (TCXO-grade) reference directly into the die. This eliminates the need for an external crystal, load capacitors, or associated PCB layout considerations. The internal reference provides stable operation across –40 to +85 °C and reduces sensitivity to acoustic noise induced by thermal ramping - a key advantage over external-crystal variants like SI5397A-A-GMR. SI5397M-A-GMR relies solely on this integrated reference; connecting an external clock to XA/XB is prohibited and may damage the device.

Does SI5397M-A-GMR support hitless switching between 25 MHz SyncE inputs?

Yes, SI5397M-A-GMR supports enhanced hitless switching between 25 MHz inputs with fixed phase relationships (e.g., 0 ppm offset or integer multiples). When enabled per DSPLL, the device absorbs phase differences during input transitions, preventing output phase transients that could disrupt downstream SerDes or packet buffers. This capability is validated per Skyworks AN1155 and meets ITU-T G.8262 requirements for carrier-grade protection switching. Hitless switching is programmable independently for each DSPLL and operates down to 8 kHz, though optimal performance is achieved at ≥25 MHz.

What output clock formats does SI5397M-A-GMR support?

SI5397M-A-GMR supports LVDS, LVPECL, CML, HCSL, and LVCMOS output formats across all four differential outputs (OUT0–OUT3). Each output is independently configurable for format, amplitude, common-mode voltage, and slew rate via register settings. This flexibility enables direct interface to diverse silicon - including FPGA transceivers (LVDS/LVPECL), ASIC SerDes (CML), and microcontrollers (LVCMOS) - without external level shifters. Output supply pins (VDDOx) accept 1.8 V, 2.5 V, or 3.3 V, allowing mixed-voltage system integration.

How is SI5397M-A-GMR programmed and configured?

SI5397M-A-GMR is programmed via I²C or SPI serial interface using Skyworks ClockBuilder Pro™ software. Configuration parameters - including input/output frequencies, DSPLL loop bandwidths, hitless switching settings, and holdover history windows - are calculated and validated in CBPro, then written to on-chip one-time-programmable (OTP) non-volatile memory. Upon power-up, SI5397M-A-GMR automatically loads this stored configuration, ensuring known-state operation without host intervention. Factory pre-programmed units (custom OPNs ending in "-GM") are also available for turnkey deployment.

What is the maximum output frequency supported by SI5397M-A-GMR?

The SI5397M-A-GMR supports a maximum differential output frequency of 350 MHz. This is specified in Skyworks' Ordering Guide (Table 3) for Grade M devices and confirmed in the Final Data Sheet Section 1 (Feature List) and Section 3 (Ordering Guides). While the Si5397 family's architecture supports up to 720 MHz (as in SI5397J-A-GMR), the M-grade variant is characterized and guaranteed for operation up to 350 MHz - a deliberate optimization for power, cost, and thermal performance in applications such as SyncE line cards and broadcast video where frequencies beyond 350 MHz are not required.

SI5397M-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5397M-A-GMR FAQ

1.How can I place an order for SI5397M-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5397M-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5397M-A-GMR reliable?

The price and inventory of SI5397M-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5397M-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5397M-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5397M-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5397M-A-GMR?

SI5397M-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5397M-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5397M-A-GMR?

For technical support, including SI5397M-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5397M-A-GMR requirements.

6.How does Aetrix verify that SI5397M-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5397M-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5397M-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5397M-A-GMR?

All SI5397M-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5397M-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5397M-A-GMR part is unused and in its original packaging.

Return procedure for SI5397M-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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