Skyworks Solutions Inc. SI8230BB-AS1R
- Part No.:
- SI8230BB-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI8230BB-AS1R.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,435
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Product details
Overview
SI8230BB-AS1R from Skyworks Solutions is an automotive-grade, high-side/low-side isolated gate driver IC with 0.5 A peak output current, 2.5 kVRMS input-to-output isolation, and TTL-compatible dual inputs (VIA/VIB). It integrates programmable dead time and overlap protection, operates up to 24 V supply, and targets half-bridge MOSFET/IGBT drive in traction inverters and onboard chargers.
For engineers reviewing the SI8230BB-AS1R datasheet, SI8230BB-AS1R pinout, SI8230BB-AS1R application, or SI8230BB-AS1R equivalent, this page delivers verified specifications, SOIC-16 narrow-body package details, automotive AEC-Q100 qualification status, and real-world use context for power stage design validation and BOM selection.
Technical Context
The SI8230BB-AS1R implements RF-based silicon isolation with a semiconductor barrier, delivering 45 ns max propagation delay and robust immunity to magnetic fields and EMI. Its two independent isolated channels support high-side and low-side gate drive with separate VDDA/VDDB supplies and individual UVLO monitoring (8 V threshold).
It features programmable dead time via external resistor (DT pin), overlap protection logic that forces both outputs low during simultaneous high inputs, and a disable function that overrides all inputs to force VOA/VOB low within tSD. Inputs are TTL-compatible with >400 mV hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 2.5 kVRMS per UL1577 - enables safe operation across reinforced insulation barriers in 400–800 V DC bus systems |
| Peak Output Current | 0.5 A - sufficient to drive medium-power MOSFETs (e.g., 10–30 nC gate charge) at ≤100 kHz switching |
| Propagation Delay | ≤45 ns - supports high-frequency PWM control up to 8 MHz with minimal timing skew between channels |
| UVLO Threshold | 8 V (VDDI, VDDA, VDDB) - prevents erratic gate drive during brown-out or soft-start conditions |
| Supply Voltage Range | 4.5–24 V - compatible with standard 5 V logic rails and 12–15 V gate drive supplies |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive environments per AEC-Q100 Grade 1 |
| Package | SOIC-16 narrow body - RoHS-compliant, JEDEC-standard footprint with 2.54 mm pitch and 1.27 mm creepage |
Pinout & Package
SOIC-16 narrow-body package (7.5 mm × 10.3 mm, 1.27 mm pitch), RoHS-compliant, peak reflow 260 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDI | Input-side power supply | Supplies isolated input logic and RF transmitter; must be ≥4.5 V for reliable operation |
| GNDI | Input-side ground reference | Reference for VIA, VIB, DISABLE, DT; galvanically separated from output grounds |
| VIA | High-side input signal | TTL-compatible, >400 mV hysteresis; controls VOA state directly |
| VIB | Low-side input signal | TTL-compatible, >400 mV hysteresis; controls VOB state directly |
| DISABLE | Global output disable | Active-high; forces VOA/VOB low regardless of VIA/VIB when asserted |
| DT | Dead time programming | Resistor-to-ground sets dead time (DT ≈ 10 × RDT ns); floating = ~400 ps nominal |
| VDDA | High-side driver supply | Power for VOA output stage; UVLO monitored independently |
| VOA | High-side gate drive output | 0.5 A source/sink; drives MOSFET gate referenced to floating high-side source |
| GNDA | High-side ground reference | Return path for VDDA and VOA; electrically isolated from GNDI and GNDB |
| VDDB | Low-side driver supply | Power for VOB output stage; UVLO monitored independently |
| VOB | Low-side gate drive output | 0.5 A source/sink; drives MOSFET gate referenced to system ground |
| GNDB | Low-side ground reference | Return path for VDDB and VOB; typically tied to system ground |
| NC | No connect | Pins 1, 16 - internally unused; must remain unconnected per datasheet |
| NC | No connect | Pins 1, 16 - internally unused; must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Dual isolated drivers in one SOIC-16 | Eliminates need for two discrete optocouplers or isolated gate drivers, reducing PCB area by >40% vs. dual-SOIC solutions |
| Programmable dead time with overlap protection | Prevents shoot-through in half-bridge topologies without external logic; resistor-tuned delay avoids fixed-timing constraints |
| Automotive-grade AEC-Q100 qualification | Validated for automotive powertrain applications including traction inverters and OBCs, with PPAP documentation support |
| RF-based silicon isolation | Delivers faster propagation (<45 ns), higher CMTI (>35 kV/µs), and better temperature stability than LED-based optocouplers |
| TTL-compatible inputs with hysteresis | Accepts direct connection to MCU GPIOs or FPGA outputs without level-shifting or external Schmitt triggers |
Applications
| Onboard Charger (OBC) | Traction Inverter |
|---|---|
Use Scenario: Isolated gate driving for bidirectional AC/DC and DC/DC stages in 6.6 kW EV onboard chargers. IC Role / Device Role / Timing Role: High-side/low-side driver controlling SiC MOSFET half-bridges in PFC and LLC resonant converters. Use Value: 2.5 kVRMS isolation meets reinforced insulation requirements for 400 V battery systems; programmable dead time ensures safe commutation under variable load and temperature. | Use Scenario: Gate drive for IGBT or SiC modules in 400–800 V battery-powered traction inverters. IC Role / Device Role / Timing Role: Dual-channel isolated driver enabling compact, high-reliability half-bridge switching with integrated shoot-through prevention. Use Value: AEC-Q100 qualification and –40 °C to +125 °C operation ensure functional safety compliance (ISO 26262 ASIL-B ready) in under-hood environments. |
| Battery Management System (BMS) | Solar Inverter |
Use Scenario: Isolated control of contactor drivers and auxiliary power stage MOSFETs in high-voltage battery packs. IC Role / Device Role / Timing Role: High-side/low-side gate driver for precharge/disconnect circuits and auxiliary DC/DC converters. Use Value: Independent UVLO on VDDI/VDDA/VDDB prevents partial operation during voltage sag; 0.5 A output supports fast contactor actuation. | Use Scenario: Gate driving for string-level or central inverters in residential/commercial PV systems with 600–1000 V DC input. IC Role / Device Role / Timing Role: Isolated driver for IGBT half-bridges in three-phase inverter legs, supporting transformerless topologies. Use Value: 2.5 kVRMS isolation satisfies IEC 62109 and UL 1741 requirements for DC side isolation; SOIC-16 narrow body enables high-density layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side/low-side isolated gate drive applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8230BD-AS | 5.0 kVRMS isolation, SOIC-16 wide body, same 0.5 A output and AEC-Q100 grade | Required where reinforced insulation demands >3.75 kVRMS (e.g., 800 V+ battery systems) | Select SI8230BD-AS when higher isolation rating is mandated by safety standards or system voltage architecture. |
| UCC21520QDWQ1 | 5.7 kVRMS isolation, 4 A peak output, dual-input, automotive AEC-Q100, but no programmable dead time | Used in high-current motor drives where 4 A drive strength is needed, but requires external dead time logic | Choose UCC21520QDWQ1 only if higher output current is required and external dead time generation is acceptable. |
Compared with SI8230BD-AS, SI8230BB-AS1R offers identical functionality and automotive qualification in a space-saving narrow-body package at lower isolation-ideal for cost- and size-constrained 400 V systems. Versus UCC21520QDWQ1, it trades peak current for integrated dead time control and simpler system-level timing design.
Availability
SI8230BB-AS1R is available at Aetrix Electronics and suitable for automotive onboard chargers, traction inverters, and solar inverters requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.
Supply support for SI8230BB-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, isolation, timing, and power management ICs for high-reliability applications.
The Si823x family was designed specifically for isolated gate driving in automotive and industrial power conversion, emphasizing integration, noise immunity, and safety certification readiness.
FAQ
What is the isolation voltage rating of the SI8230BB-AS1R?
The SI8230BB-AS1R provides 2.5 kVRMS input-to-output isolation per UL1577, validated for one minute. This rating supports reinforced insulation in 400 V DC bus systems and complies with IEC 62368-1 and GB4943.1 requirements. It is not rated for 5.0 kVRMS applications - for those, SI8230BD-AS is specified.
Does the SI8230BB-AS1R support programmable dead time?
Yes, the SI8230BB-AS1R supports programmable dead time via the DT pin. A resistor (RDT) connected from DT to ground sets the delay using DT ≈ 10 × RDT (ns). Floating the DT pin yields ~400 ps nominal dead time. This feature is integral to the SI8230BB-AS1R's overlap protection and eliminates external timing circuitry in half-bridge designs.
Is the SI8230BB-AS1R qualified for automotive applications?
Yes, the SI8230BB-AS1R is automotive-grade and AEC-Q100 qualified (Grade 1, –40 °C to +125 °C). Its part number suffix "-AS1R" confirms automotive process flow, AIAG-compliant PPAP documentation, and IMDS/CAMDS material reporting - making it suitable for OBC, BMS, and traction inverter use.
What are the UVLO thresholds for the SI8230BB-AS1R?
The SI8230BB-AS1R has independent UVLO monitors: VDDI, VDDA, and VDDB each trigger at 8 V (rising) and 7.5 V (falling). When any supply drops below its UVLO threshold, the corresponding channel disables and forces its output low. This behavior is confirmed in the datasheet's Section 2.6 and applies identically across all SI8230BB-AS1R units.
Can the SI8230BB-AS1R drive both high-side and low-side MOSFETs simultaneously?
Yes - the SI8230BB-AS1R is explicitly configured as a high-side/low-side driver with dedicated VOA (high-side) and VOB (low-side) outputs. Its truth table (Table 3) and block diagram (Figure 1) confirm independent control of both outputs via VIA and VIB, with built-in overlap protection preventing simultaneous conduction.
SI8230BB-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 20kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 45ns, 45ns
- Pulse Width Distortion (Max):
- 5.6ns
- Rise / Fall Time (Typ):
- 20ns, 20ns (Max)
- Current - Output High, Low:
- 250mA, 500mA
- Current - Peak Output:
- 500mA
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 6.5V ~ 24V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UL, VDE
SI8230BB-AS1R FAQ
1.How can I place an order for SI8230BB-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8230BB-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8230BB-AS1R reliable?
The price and inventory of SI8230BB-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8230BB-AS1R is usually 5 days.
3.What payment methods are accepted for SI8230BB-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8230BB-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8230BB-AS1R?
SI8230BB-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8230BB-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8230BB-AS1R?
For technical support, including SI8230BB-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8230BB-AS1R requirements.
6.How does Aetrix verify that SI8230BB-AS1R is sourced from the original manufacturer or authorized distributors?
All SI8230BB-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8230BB-AS1R meets industry standards.
7.What is the process for return or replacement of SI8230BB-AS1R?
All SI8230BB-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI8230BB-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8230BB-AS1R part is unused and in its original packaging.
Return procedure for SI8230BB-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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