My Inquiry
My Account
Skyworks Solutions Inc. SI82391AD-IS3R
- Part No.:
- SI82391AD-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 14-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI82391AD-IS3R.pdf
- Description:
- DGT ISO 3.25KV 2CH GT DVR 14SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,859
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI82391AD-IS3R from Skyworks Solutions is a dual-channel isolated gate driver IC designed for high-side/low-side MOSFET and IGBT control in power converters. It delivers 4.0 A peak output current, operates with 2.5 V–5.5 V input supply (VDDI), supports up to 5 kVRMS isolation, and features enhanced output UVLO with status feedback. It is used in solar inverters, motor drives, and isolated DC-DC supplies where robust isolation and fault-aware gate driving are critical.
For engineers reviewing the SI82391AD-IS3R datasheet, SI82391AD-IS3R pinout, SI82391AD-IS3R application, or SI82391AD-IS3R equivalent, key selection considerations include its SOIC-14 wide-body package, 30 ns propagation delay, programmable dead time (10–200 ns), fail-safe low-default outputs during VDDI power-down, and compatibility with industrial and automotive-grade system requirements per AEC-Q100.
Technical Context
The SI82391AD-IS3R implements RF-based on/off keying across a silicon isolation barrier-replacing optocoupler-based architectures with higher CMTI (100 kV/µs), lower propagation skew, and improved temperature stability. Its two independent isolated channels accept separate VIA/VIB inputs and drive high-side and low-side power switches with independent UVLO monitoring on each output supply rail (VDDA/VDDB).
This variant belongs to the Si8239x "enhanced UVLO with status" subfamily (Si82390/1/3). It provides bidirectional UVLO fault detection: when either VDDA or VDDB falls below its threshold, the corresponding output (VOA or VOB) is actively driven low, and that fault state is fed back across isolation to the input side logic-enabling transformer flux balance protection in half-bridge topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5 kVRMS withstand voltage - enables reinforced insulation per IEC 62368-1 and UL 1577 for safety-critical power systems. |
| Peak Output Current | 4.0 A - sufficient to rapidly charge/discharge high-Qg MOSFETs and IGBTs in hard-switched topologies up to 100 kHz. |
| Propagation Delay | 30 ns - ensures precise timing alignment between high-side and low-side drivers, minimizing shoot-through risk in bridge circuits. |
| VDDI Supply Range | 2.5 V–5.5 V - compatible with modern low-voltage microcontrollers and FPGAs without level-shifting. |
| UVLO Threshold (VDDA/VDDB) | 6 V (typical) - prevents erratic switching during brown-out conditions; fault feedback forces corresponding output low. |
| Dead Time Programmability | 10–200 ns - configurable via external resistor to optimize overlap margin without requiring controller-level dead-time insertion. |
| Operating Temperature | –40 °C to +125 °C - validated for under-hood automotive and industrial ambient environments. |
Pinout & Package
SI82391AD-IS3R is housed in a RoHS-compliant SOIC-14 wide-body package (7.5 mm body width, 10.3 mm length), rated for 260 °C peak reflow per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Input A | TTL-compatible high-true logic input controlling VOA; referenced to GNDI. |
| VIB | Input B | TTL-compatible high-true logic input controlling VOB; referenced to GNDI. |
| EN | Enable Input | Active-high global shutdown: forces both VOA and VOB low regardless of VIA/VIB states when pulled low. |
| VDDI | Input-Side Supply | 2.5 V–5.5 V power for input logic and isolation transmitter; includes internal UVLO (VDDIUV– = 2.1 V typ). |
| GNDI | Input Ground | Reference for VIA, VIB, EN, VDDI, and RDY; galvanically isolated from power-side ground. |
| RDY | Ready Status Output | Open-drain digital flag indicating valid operation after safe startup delay (~1 ms); pulled low during UVLO or EN = L. |
| VDDA | Driver A Supply | 10 V–24 V supply for high-side driver output stage; monitored for UVLO (6 V threshold). |
| VOA | Output A | 4.0 A capable high-side gate driver output; defaults low if VDDI unpowered or VDDA in UVLO. |
| GND1 | Driver A Ground | Power-side ground reference for VDDA and VOA; isolated from GNDI and GND2. |
| VDDB | Driver B Supply | 10 V–24 V supply for low-side driver output stage; monitored for UVLO (6 V threshold). |
| VOB | Output B | 4.0 A capable low-side gate driver output; defaults low if VDDI unpowered or VDDB in UVLO. |
| GND2 | Driver B Ground | Power-side ground reference for VDDB and VOB; isolated from GNDI and GND1. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced UVLO with cross-isolation feedback | When VDDA or VDDB drops below 6 V, the corresponding output (VOA/VOB) is actively driven low *and* that fault condition is reported to input-side logic-enabling coordinated shutdown in half-bridge configurations. |
| Fail-safe default-low outputs | Both VOA and VOB remain low during VDDI power-down or EN = L, preventing unintended power device turn-on in fault or reset conditions. |
| Programmable dead time (10–200 ns) | Eliminates need for external timing components or controller firmware dead-time compensation-reduces design complexity and improves reliability in high-frequency bridges. |
| 1 ms safe delayed startup | Guarantees monotonic output behavior during power-up: VOA/VOB remain low until VDDI stabilizes and internal logic completes initialization. |
| High CMTI (100 kV/µs) | Resists fast transient noise in high-dV/dt environments (e.g., SiC/GaN inverters), maintaining signal integrity without false triggering. |
Applications
| Solar Inverter Half-Bridge | Industrial Motor Drive H-Bridge |
|---|---|
Use Scenario: Controlling high-voltage IGBTs in a 1000 V DC-link solar inverter half-bridge stage with transformerless topology. IC Role / Device Role / Timing Role: Isolated high-side/low-side gate driver providing independent UVLO monitoring per leg and cross-isolation fault reporting to prevent transformer saturation. Use Value: Enables reliable operation at 16 kHz switching with <30 ns channel-to-channel skew and automatic flux-balancing response to asymmetric rail faults. |
Use Scenario: Driving 600 V, 50 A IGBTs in a 3-phase industrial servo drive inverter module. IC Role / Device Role / Timing Role: Dual isolated driver delivering 4.0 A peak current per channel with programmable 100 ns dead time to prevent shoot-through during PWM transitions. Use Value: Reduces gate drive loop inductance via SOIC-14 wide-body layout and eliminates need for external dead-time circuitry, improving EMI performance and thermal margin. |
| On-Board EV Charger | Battery Management System Isolation |
Use Scenario: Gate driving SiC MOSFETs in a 3.3 kW AC/DC OBC PFC and LLC stage operating at 100–300 kHz. IC Role / Device Role / Timing Role: High-CMTI isolated driver supporting fast 30 ns propagation and 100 kV/µs transient immunity in noisy high-frequency power conversion. Use Value: Maintains clean switching edges despite >50 V/ns common-mode transients from adjacent power stages, reducing gate oscillation and RFI. |
Use Scenario: Providing isolated gate control for active balancing FETs in a 400 V battery pack with distributed cell monitoring. IC Role / Device Role / Timing Role: Fail-safe isolated driver ensuring all balancing switches default OFF during MCU reset or supply brown-out. Use Value: Prevents uncontrolled energy discharge through balancing FETs during power sequencing faults-critical for ASIL-B functional safety compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI82331BD-IS3R | Same SOIC-14 WB package, 4 A drive, but lacks enhanced UVLO feedback; only local UVLO per channel without cross-isolation reporting. | Not suitable for transformer-coupled topologies requiring flux balance; acceptable for standard half-bridge where independent rail monitoring suffices. | Select when cost sensitivity outweighs need for fault coordination across isolation barrier; verify system-level UVLO handling in controller. |
| UCC5390SCDR | TI part with 5 A drive, integrated deglitch, but only 3.75 kVRMS isolation and no programmable dead time; requires external RC network for delay tuning. | Lower isolation rating limits use in reinforced-insulation systems; deglitch helps in noisy environments but adds component count. | Prefer for high-noise industrial PLCs where deglitch filtering is prioritized over transformer flux protection or dead-time precision. |
Compared with SI82391AD-IS3R, SI82331BD-IS3R omits cross-isolation UVLO feedback-reducing fault coordination capability but lowering BOM cost-while UCC5390SCDR trades isolation strength and dead-time flexibility for integrated noise filtering, making it better suited for non-safety-critical, high-EMI applications.
Availability
SI82391AD-IS3R is available at Aetrix Electronics and suitable for solar inverters, traction motor drives, and on-board EV chargers requiring stable component supply, AEC-Q100 qualified assurance, and long-term industrial lifecycle support.
Supply support for SI82391AD-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.
The Si8239x family was engineered specifically for isolated gate driving in high-power, high-reliability systems-including automotive traction inverters and industrial motor controls-leveraging proprietary silicon isolation to replace aging optocoupler-based designs.
FAQ
What is the isolation voltage rating of the SI82391AD-IS3R?
The SI82391AD-IS3R is rated for 5 kVRMS isolation withstand voltage per UL 1577 and IEC 62368-1, supporting reinforced insulation in safety-critical power systems. This rating applies across the full operating temperature range (–40 °C to +125 °C) and is validated for 1 minute per safety agency test protocols. The isolation barrier uses Skyworks' proprietary silicon technology-not optocouplers-ensuring stable performance over time and temperature.
Does the SI82391AD-IS3R support bootstrap power supply configurations?
No, the SI82391AD-IS3R does not support bootstrap power supply configurations. Its enhanced UVLO architecture requires independent, regulated VDDA and VDDB supplies. Using a bootstrap circuit violates the requirement for independent rail monitoring and disables cross-isolation UVLO feedback-potentially causing transformer flux imbalance in half-bridge topologies. SI82391AD-IS3R must be powered from isolated DC-DC supplies or dedicated bias rails.
How does the RDY pin function on the SI82391AD-IS3R?
The RDY pin on the SI82391AD-IS3R is an open-drain status output that goes high-impedance (pull-up required externally) when the device completes its 1 ms safe startup sequence and all supplies (VDDI, VDDA, VDDB) are within UVLO thresholds. It pulls low during VDDI undervoltage, EN = L, or any output UVLO event. This pin enables system-level readiness verification before enabling PWM generation in controllers.
What is the purpose of the EN pin on the SI82391AD-IS3R?
The EN (enable) pin on the SI82391AD-IS3R is an active-high global shutdown control. When pulled low (via 100 kΩ resistor to GNDI), it forces both VOA and VOB low within tSD (shutdown delay), overriding VIA/VIB inputs. It has no effect if VDDI is below UVLO. This pin enables hardware-level fault containment-for example, tying EN to a microcontroller's fault interrupt output or an overtemperature comparator signal.
Can the SI82391AD-IS3R drive SiC MOSFETs effectively?
Yes, the SI82391AD-IS3R can effectively drive SiC MOSFETs. Its 4.0 A peak output current, 30 ns propagation delay, and 100 kV/µs CMTI meet the demanding gate drive requirements of 650 V–1200 V SiC devices. The SOIC-14 wide-body package minimizes parasitic inductance, and the programmable 10–200 ns dead time allows precise optimization for SiC's fast switching transitions-reducing switching losses and EMI without external timing components.
SI82391AD-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 14-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 3250Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 40ns, 40ns
- Pulse Width Distortion (Max):
- 5.6ns
- Rise / Fall Time (Typ):
- 12ns, 12ns (Max)
- Current - Output High, Low:
- 2A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 6.5V ~ 24V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
- Approval Agency:
- CQC, CSA, UR, VDE
SI82391AD-IS3R FAQ
1.How can I place an order for SI82391AD-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82391AD-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82391AD-IS3R reliable?
The price and inventory of SI82391AD-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82391AD-IS3R is usually 5 days.
3.What payment methods are accepted for SI82391AD-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82391AD-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82391AD-IS3R?
SI82391AD-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82391AD-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82391AD-IS3R?
For technical support, including SI82391AD-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82391AD-IS3R requirements.
6.How does Aetrix verify that SI82391AD-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82391AD-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82391AD-IS3R meets industry standards.
7.What is the process for return or replacement of SI82391AD-IS3R?
All SI82391AD-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82391AD-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82391AD-IS3R part is unused and in its original packaging.
Return procedure for SI82391AD-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI82391AD-IS3R Tags
.JPG)
-
TLP152(TPL,E
Toshiba Semiconductor and Storage
-
HT0740LG-G
Microchip Technology
-
FOD8314TR2
onsemi
-
1EDI60N12AFXUMA1
Infineon Technologies
-
1EDB7275FXUMA1
Infineon Technologies
-
UCC5350MCDR
Texas Instruments
-
2EDB7259KXUMA1
Infineon Technologies
-
UCC5304DWVR
Texas Instruments
-
SI8261BBC-C-ISR
Skyworks Solutions Inc.
-
HT0440LG-G
Microchip Technology
-
HCPL-0302-500E
Broadcom Limited
-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
