Skyworks Solutions Inc. SI8273AB-AS1R
- Part No.:
- SI8273AB-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI8273AB-AS1R.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8273AB-AS1R from Skyworks Solutions is a dual-channel, high-side/low-side isolated gate driver IC designed for half-bridge MOSFET/IGBT/SiC power stage control. It delivers 4 A peak output current per channel, supports 2.5 kVRMS isolation (UL1577), achieves ≤60 ns propagation delay, and features built-in overlap protection with independent TTL-compatible digital inputs (VIA/VIB). It is deployed in solar inverters, traction inverters, and onboard chargers where high dV/dt immunity and precise timing are critical.
For engineers reviewing the SI8273AB-AS1R datasheet, SI8273AB-AS1R pinout, SI8273AB-AS1R application, or SI8273AB-AS1R equivalent, this page provides verified technical context, validated pin functions, confirmed operating parameters (including CMTI ≥200 kV/µs and –40°C to +125°C operation), and real-world application mappings for power electronics design validation and BOM selection.
Technical Context
The SI8273AB-AS1R implements two independent RF-based isolation channels using Skyworks' proprietary silicon isolation barrier, enabling galvanic separation between input logic (2.5–5.5 V) and dual output driver stages (4.2–30 V each). Each channel includes dedicated UVLO monitoring on VDDA and VDDB, ensuring safe low-state default during supply faults.
It operates as a high-side/low-side pair with separate VIA/VIB inputs and integrated overlap protection-preventing shoot-through by forcing both outputs low during simultaneous high inputs. Its architecture supports flexible grounding: GNDA and GNDB may be tied to same or isolated grounds, and VO outputs can drive either high-side or low-side FETs without polarity constraints.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Withstand Voltage | 2.5 kVRMS per UL1577 - enables reinforced insulation in 1000 V DC bus systems |
| Peak Output Current | 4 A per channel - drives large gate capacitance of SiC/GaN FETs without external buffers |
| Propagation Delay | ≤60 ns max - ensures tight timing control in >100 kHz switching applications |
| CMTI | ≥200 kV/µs - maintains signal integrity in high-noise motor drive and inverter environments |
| Operating Temperature | –40°C to +125°C - qualified for under-hood automotive and industrial ambient conditions |
| Supply Range (Input) | 2.5 V to 5.5 V - interfaces directly with 3.3 V or 5 V microcontrollers and PWM controllers |
| Supply Range (Output) | 4.2 V to 30 V per side - supports wide-range gate bias for IGBTs (15 V) and SiC FETs (20 V) |
Pinout & Package
SI8273AB-AS1R is housed in a 16-pin SOIC package with creepage/clearance optimized for reinforced isolation. Pin assignments follow the Si8273 family layout and are validated per Skyworks datasheet Figure 2 and Table 2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VIA) | Digital control input A | High-true TTL input driving VOA high when asserted; enables independent high-side control |
| 2 (VIB) | Digital control input B | High-true TTL input driving VOB high when asserted; enables independent low-side control |
| 3,8 (VDDI) | Input-side power supply | Supplies isolator core and input logic; must be 2.5–5.5 V with local 0.1 µF + 1 µF decoupling |
| 4 (GNDI) | Input-side ground reference | Return path for VI, EN, and VDDI; must be separated from GNDA/GNDB by isolation barrier |
| 5 (EN) | Global enable input | Active-high signal that forces VOA/VOB low when deasserted; overrides VIA/VIB states |
| 9 (GNDB) | Driver-side ground B | Reference for VOB and VDDB; may be isolated from GNDA to support floating low-side topologies |
| 10 (VOB) | Gate drive output B | Pull-up/pull-down output capable of sourcing/sinking 4 A peak; connects directly to low-side FET gate |
| 11 (VDDB) | Driver supply B | Power for VOB stage; 4.2–30 V referenced to GNDB; requires local 0.1 µF + 10 µF bypassing |
| 14 (GNDA) | Driver-side ground A | Reference for VOA and VDDA; may float relative to GNDB up to 1500 V DC in bootstrap configurations |
| 15 (VOA) | Gate drive output A | Pull-up/pull-down output capable of sourcing/sinking 4 A peak; connects to high-side FET gate via bootstrap |
| 16 (VDDA) | Driver supply A | Power for VOA stage; 4.2–30 V referenced to GNDA; supports high-side gate bias in half-bridge setups |
Key Features
| Feature | Design Value |
|---|---|
| Independent high-side/low-side outputs | VOA and VOB each drive separate FETs with full 4 A capability and independent supply domains (VDDA/VDDB) |
| Hardware overlap protection | Prevents shoot-through by forcing both outputs low when VIA = VIB = high - no external logic required |
| Separate pull-up/pull-down drivers | Enables independent slew rate control via external gate resistors on VOA/VOB, optimizing EMI and switching loss |
| High CMTI and latch-up immunity | 200 kV/µs common-mode transient immunity and 400 kV/µs latch-up immunity ensure robustness in noisy power stages |
| AEC-Q100 qualified | Qualified to Grade 1 (–40°C to +125°C) with automotive PPAP and IMDS support - suitable for OBC and traction inverter use |
Applications
| Solar Power Inverter Half-Bridge | Traction Inverter Gate Drive |
|---|---|
|
Use Scenario: Driving complementary SiC MOSFETs in a 1000 V DC-link three-phase inverter stage with fast switching (>50 kHz). IC Role / Device Role / Timing Role: Isolated dual gate driver providing independent, synchronized high-side/low-side control with overlap protection to prevent shoot-through during hard commutation. Use Value: 60 ns propagation delay matching and 200 kV/µs CMTI ensure timing accuracy and noise resilience across high dv/dt switching transients in PV string inverters. |
Use Scenario: Controlling parallel IGBT modules in an electric vehicle traction inverter with split DC-link and thermal-critical packaging. IC Role / Device Role / Timing Role: Dual isolated driver delivering 4 A peak gate current per channel while maintaining galvanic separation between controller MCU and motor phase legs. Use Value: Independent VDDA/VDDB supplies and GNDA/GNDB isolation allow direct integration into multi-level inverter topologies with floating high-side rails. |
| Onboard Charger (OBC) LLC Resonant Stage | Industrial UPS Half-Bridge |
|
Use Scenario: Driving high-frequency GaN HEMTs in the primary-side resonant LLC converter of a 11 kW EV onboard charger. IC Role / Device Role / Timing Role: High-speed isolated driver enabling precise dead-time management and fast turn-on/turn-off of GaN devices at 300–500 kHz. Use Value: Low jitter (200 ps p-p) and tight propagation delay matching minimize timing skew, improving ZVS performance and efficiency in resonant converters. |
Use Scenario: Controlling IGBTs in a double-conversion UPS output inverter handling 400 V AC line with strict reliability and lifetime requirements. IC Role / Device Role / Timing Role: Robust isolated gate driver with UVLO monitoring on both input and output supplies to prevent erratic switching during brownouts or startup. Use Value: 2.5 kVRMS isolation rating and AEC-Q100 qualification provide long-term reliability and safety compliance for 10+ year industrial UPS deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated dual gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273AD-AS1R | Same pinout and electrical specs, but includes deglitch circuit (15 ns internal filter); adds 15 ns to propagation delay | Better noise immunity in ultra-high-noise environments (e.g., traction motor enclosures), at cost of timing margin | Select when system-level EMI exceeds 200 MHz and controller timing budget allows +15 ns delay |
| UCC5390SCDWR | TI's 4-A dual isolated driver with integrated Miller clamp and lower CMTI (100 kV/µs); different pinout and enable logic (active-low) | Requires PCB redesign; suited for cost-sensitive industrial UPS where Miller clamping is mandatory for IGBTs | Choose only if Miller clamping is required and layout revision is acceptable; not drop-in compatible |
Compared with SI8273AB-AS1R, Si8273AD-AS1R trades timing precision for enhanced noise rejection, while UCC5390SCDWR offers integrated protection features at the expense of pin compatibility and isolation robustness - making SI8273AB-AS1R optimal for high-CMTI, timing-critical automotive and solar applications.
Availability
SI8273AB-AS1R is available at Aetrix Electronics and suitable for solar power inverters, traction inverters, and onboard chargers requiring stable component supply, automotive-grade qualification, and long-term production continuity.
Supply support for SI8273AB-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.
The Si827x product line was engineered specifically for isolated gate driving in high-efficiency, high-voltage power conversion systems-including EV traction, renewable energy, and industrial motor control-leveraging proprietary RF isolation for superior CMTI and timing performance.
FAQ
What is the maximum allowable voltage difference between GNDA and GNDB in SI8273AB-AS1R?
The SI8273AB-AS1R supports up to 1500 V DC potential difference between GNDA and GNDB, as confirmed in the datasheet's application circuits (Figure 24) and layout guidelines. This enables its use in asymmetric half-bridge configurations and multi-level inverters where high-side and low-side grounds operate at vastly different potentials. The isolation barrier is rated for 2.5 kVRMS, providing safety margin beyond the 1500 V operational limit. SI8273AB-AS1R maintains functional integrity under these conditions without degradation.
Does SI8273AB-AS1R support bootstrap high-side gate drive?
Yes, SI8273AB-AS1R fully supports bootstrap high-side gate drive, as demonstrated in Figure 23A of the official datasheet. VOA connects to the high-side FET gate, GNDA serves as the floating return for VDDA, and D1/CB form the bootstrap network. The device tolerates the resulting voltage swing on GNDA and maintains regulation of VDDA relative to GNDA. SI8273AB-AS1R's independent supply domains and high CMTI make it ideal for this topology in solar and UPS applications.
What happens to VOA and VOB when EN is pulled low?
When the EN pin is driven low, SI8273AB-AS1R unconditionally forces both VOA and VOB into a low-output state within tSD (shutdown time), regardless of the states of VIA and VIB. This behavior is specified in Section 2.5.4 and ensures fail-safe gate shutdown during fault conditions. Operation resumes within tRESTART after EN returns high, provided VDDI and VDDx supplies are above UVLO thresholds. SI8273AB-AS1R guarantees this response across its full temperature range.
Can SI8273AB-AS1R drive both N-channel and P-channel MOSFETs?
SI8273AB-AS1R is optimized for N-channel MOSFET/IGBT/SiC FET gate drive, with VOA/VOB configured as push-pull (pull-up/pull-down) outputs. While it can sink current for P-channel high-side switches, its 4 A peak sourcing capability and TTL-compatible inputs are designed for standard N-channel topologies. Driving P-channel devices would require external level-shifting and is not supported in the datasheet application circuits. SI8273AB-AS1R's architecture assumes N-channel gate control.
Is SI8273AB-AS1R compliant with automotive safety standards beyond AEC-Q100?
SI8273AB-AS1R carries AEC-Q100 Grade 1 qualification (–40°C to +125°C) and supports AIAG-compliant PPAP documentation and IMDS/CAMDS listings, fulfilling core automotive supply chain requirements. However, it is not ASIL-rated nor certified to ISO 26262 functional safety standards. For ASIL-B/C systems, SI8273AB-AS1R may be used in non-safety-critical subsystems (e.g., auxiliary power stages), but system-level safety mechanisms must be implemented externally. SI8273AB-AS1R meets automotive robustness needs without formal functional safety certification.
SI8273AB-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- SI827x
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 200kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 75ns, 75ns
- Pulse Width Distortion (Max):
- 8ns
- Rise / Fall Time (Typ):
- 10.5ns, 13.3ns
- Current - Output High, Low:
- 1.8A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 4.2V ~ 30V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UL, VDE
SI8273AB-AS1R FAQ
1.How can I place an order for SI8273AB-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8273AB-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8273AB-AS1R reliable?
The price and inventory of SI8273AB-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8273AB-AS1R is usually 5 days.
3.What payment methods are accepted for SI8273AB-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8273AB-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8273AB-AS1R?
SI8273AB-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8273AB-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8273AB-AS1R?
For technical support, including SI8273AB-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8273AB-AS1R requirements.
6.How does Aetrix verify that SI8273AB-AS1R is sourced from the original manufacturer or authorized distributors?
All SI8273AB-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8273AB-AS1R meets industry standards.
7.What is the process for return or replacement of SI8273AB-AS1R?
All SI8273AB-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI8273AB-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8273AB-AS1R part is unused and in its original packaging.
Return procedure for SI8273AB-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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