Skyworks Solutions Inc. SI8274BB1-AS1R
- Part No.:
- SI8274BB1-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI8274BB1-AS1R.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8274BB1-AS1R from Skyworks Solutions is a dual-channel isolated PWM gate driver IC designed for high-side/low-side MOSFET/IGBT/SiC/GaN FET control in half-bridge topologies. It delivers 4 A peak output current per channel, supports 2.5 kVRMS isolation (UL1577), achieves ≤60 ns propagation delay, and features programmable dead-time control via external resistor. It operates across –40°C to +125°C and is AEC-Q100 qualified for automotive traction inverters and onboard chargers.
For engineers reviewing the SI8274BB1-AS1R datasheet, SI8274BB1-AS1R pinout, SI8274BB1-AS1R application, or SI8274BB1-AS1R equivalent, key selection criteria include its 200 kV/µs CMTI rating, separate VOA/VOB pull-up/pull-down outputs for slew-rate tuning, TTL-compatible PWM input with >400 mV hysteresis, and integrated overlap protection - all critical for reliable SiC/GaN switching in high-dV/dt motor drives and solar inverters.
Technical Context
The SI8274BB1-AS1R implements RF-based silicon isolation with a modulated carrier architecture, enabling robust noise immunity without optical degradation. Its dual-output structure provides independent high-side (VOA) and low-side (VOB) gate drive paths, each with dedicated supply rails (VDDA/GNDA and VDDB/GNDB) and UVLO monitoring.
It integrates programmable dead-time control via the DT pin (6–100 kΩ resistor to GNDI), delivering 10–700 ns user-adjustable delay between VOA and VOB transitions. The device enforces overlap protection by design: when PWM = HIGH, VOA = HIGH and VOB = LOW; when PWM = LOW, VOA = LOW and VOB = HIGH - eliminating shoot-through risk without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Withstand Voltage | 2.5 kVRMS per UL1577 - enables reinforced insulation in 1000 V DC bus systems |
| Peak Output Current | 4 A per channel - sufficient to directly drive 1000 V SiC MOSFETs with <10 nC gate charge |
| Propagation Delay | ≤60 ns max - supports >1 MHz switching frequencies with tight timing control |
| CMTI Rating | 200 kV/µs - ensures reliable operation in high-di/dt environments like traction inverters |
| Supply Range (Input) | 2.5–5.5 V - compatible with 3.3 V and 5 V microcontrollers and FPGA I/O |
| Supply Range (Output) | 4.2–30 V per channel - supports gate drive for IGBTs (15 V), SiC (12–20 V), and GaN (5–6 V) |
| Dead-Time Programmability | 10–700 ns via RDT - eliminates need for external dead-time circuits in half-bridge designs |
Pinout & Package
SI8274BB1-AS1R is housed in a 16-pin SOIC package with wide creepage/clearance for reinforced isolation. Pin assignments are defined per Skyworks datasheet revision 206327E (Jan 2026).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | PWM | TTL-compatible pulse-width modulation input - controls complementary VOA/VOB states |
| 3, 8 | VDDI | Input-side logic supply - powers isolation transmitter and EN/DT circuitry |
| 4 | GNDI | Input-side reference ground - must be isolated from driver-side grounds |
| 5 | EN | Active-high enable - forces both VOA and VOB low when deasserted |
| 6 | DT | Dead-time programming input - connects to GNDI via resistor to set inter-channel delay |
| 9, 11 | GNDB, VDDB | Low-side driver ground and supply - independent rail for VOB output stage |
| 14, 15, 16 | GNDA, VOA, VDDA | High-side driver ground, output, and supply - independent rail for VOA output stage |
Key Features
| Feature | Design Value |
|---|---|
| RF-based silicon isolation | Eliminates LED aging and temperature drift of optocouplers - ensures stable timing over life and temperature |
| Separate pull-up/pull-down outputs | Enables independent gate resistor placement on VOA/VOB for optimized turn-on/turn-off slew rates |
| Dedicated EN pin with fast disable | Terminates gate drive within tSD (typ. 100 ns) - critical for fault shutdown in EV inverters |
| Programmable dead time | Configurable 10–700 ns delay prevents shoot-through without external logic or MCU intervention |
| AEC-Q100 Grade 1 qualification | Validated for –40°C to +125°C operation with PPAP support - meets automotive functional safety requirements |
Applications
| Motor Control in EV Traction Inverters | Solar Power String Inverters |
|---|---|
Use Scenario: Driving parallel SiC MOSFET half-bridges in 800 V battery systems with >10 kHz PWM and >50 kV/µs common-mode transients. IC Role / Device Role / Timing Role: Isolated PWM-to-complementary-gate-drive translator with programmable dead time and UVLO-protected output stages. Use Value: 200 kV/µs CMTI and 60 ns propagation delay ensure precise, jitter-free switching under high di/dt conditions - reducing EMI and improving inverter efficiency. |
Use Scenario: Controlling high-voltage IGBTs in transformerless string inverters operating at 1000 V DC bus with rapid grid fault response. IC Role / Device Role / Timing Role: Reinforced-isolation gate driver providing galvanic separation between MCU control domain and power stage. Use Value: 2.5 kVRMS withstand voltage and AEC-Q100 qualification enable long-term reliability in outdoor, ungrounded PV installations. |
| Onboard Charger (OBC) Bidirectional Converters | Industrial UPS Half-Bridge Stages |
Use Scenario: Managing synchronous rectification and active switching in CLLC resonant converters with bidirectional power flow. IC Role / Device Role / Timing Role: Dual-channel isolated driver coordinating high-side/low-side FETs with adaptive dead time to minimize conduction loss. Use Value: Independent VDDA/VDDB supplies allow asymmetric gate voltages (e.g., 18 V for SiC turn-on, 5 V for GaN turn-off), optimizing switching losses. |
Use Scenario: Driving 600 V IGBTs in double-conversion UPS systems requiring fail-safe shutdown during AC mains failure. IC Role / Device Role / Timing Role: Fault-tolerant gate driver with EN-controlled hard disable and UVLO-locked outputs during brownout. Use Value: Dedicated EN pin and per-rail UVLO prevent partial drive during supply collapse - avoiding shoot-through and device destruction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated PWM gate drive applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8274AD1-AS1R | Same pinout and function, but rated for –55°C to +125°C (ZS suffix); higher-grade screening for extended automotive use | Required for under-hood traction inverter modules where ambient exceeds –40°C lower limit | Select when full AEC-Q100 Grade 0 compliance and extended temperature range are mandatory |
| UCC5390SCDR | TI part with 4 A peak drive, 3.75 kVRMS isolation, but fixed 100 ns dead time and no DT pin; uses capacitive isolation | Lacks programmable dead time - requires MCU-level timing compensation in variable-frequency resonant converters | Choose if system-level dead time is fixed and UL certification suffices over VDE/CSA approvals |
Compared with SI8274BB1-AS1R, Si8274AD1-AS1R offers extended temperature capability for harsher automotive zones, while UCC5390SCDR trades programmability for higher isolation rating and different isolation technology - making SI8274BB1-AS1R optimal for cost-sensitive, flexible dead-time tuning in industrial and mainstream automotive OBCs.
Availability
SI8274BB1-AS1R is available at Aetrix Electronics and suitable for automotive onboard chargers, solar string inverters, and industrial UPS systems requiring stable component supply, long-lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for SI8274BB1-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, isolation, and precision timing technologies.
The Si827x family was engineered specifically for high-reliability isolated gate driving in next-generation power electronics - targeting SiC/GaN adoption in EVs, renewable energy, and industrial motor drives with superior CMTI, timing stability, and lifetime performance versus optocouplers.
FAQ
What is the isolation rating and safety certification status of the SI8274BB1-AS1R?
The SI8274BB1-AS1R provides 2.5 kVRMS withstand voltage per UL1577 and carries UL recognition, CSA 62368-1 (basic insulation), VDE 60747-17 (basic insulation), and CQC GB4943.1 certifications. These approvals validate its suitability for reinforced insulation in 1000 V DC systems such as solar inverters and EV traction drives - no additional external isolation components are required for compliance.
How does the dead-time control work on the SI8274BB1-AS1R, and what resistor value gives 200 ns?
The SI8274BB1-AS1R uses an external resistor (RDT) from the DT pin to GNDI to set dead time. For the 10–200 ns range, DT = 2.02 × RDT + 7.77 (ns). To achieve 200 ns, RDT ≈ 95.5 kΩ - a standard 95.3 kΩ or 100 kΩ resistor is recommended. A 0.1 µF ceramic capacitor must be placed in parallel with RDT near the DT pin for noise immunity.
Can the SI8274BB1-AS1R drive both SiC MOSFETs and IGBTs, and what supply voltages are supported?
Yes, the SI8274BB1-AS1R supports both SiC MOSFETs and IGBTs. Its output supply range is 4.2–30 V per channel (VDDA/VDDB), enabling 12–20 V gate drive for SiC devices and 15 V for IGBTs. Input-side logic operates from 2.5–5.5 V, matching standard MCU/FPGA I/O levels - making SI8274BB1-AS1R adaptable across multiple power semiconductor technologies.
What happens to the outputs during undervoltage lockout (UVLO) on the SI8274BB1-AS1R?
During UVLO, the SI8274BB1-AS1R forces both VOA and VOB low regardless of PWM state. Each side has independent UVLO: VDDI < 2.1 V triggers input-side lockout; VDDA or VDDB < 3.7 V triggers corresponding output-side lockout. Outputs remain low until all supplies exceed their UVLO thresholds and tSTART (typically 1 µs) elapses - preventing erratic switching during power-up/down.
Is the SI8274BB1-AS1R pin-compatible with other Si827x variants like the Si8273 or Si8275?
No, the SI8274BB1-AS1R is not pin-compatible with Si8273 or Si8275. While all share the 16-pin SOIC package, pin functions differ: SI8274 uses PWM and DT pins (pins 1 and 6), whereas Si8273 uses VIA/VIB (pins 1 and 2) and Si8275 uses VIA/VIB (pins 1 and 2) without DT. PCB layout must be specific to SI8274BB1-AS1R - no mechanical or electrical interchangeability exists.
SI8274BB1-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- SI827x
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- RF Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 200kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 105ns, 75ns
- Pulse Width Distortion (Max):
- 47ns
- Rise / Fall Time (Typ):
- 10.5ns, 13.3ns
- Current - Output High, Low:
- 1.8A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 4.2V ~ 30V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UL, VDE
SI8274BB1-AS1R FAQ
1.How can I place an order for SI8274BB1-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8274BB1-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8274BB1-AS1R reliable?
The price and inventory of SI8274BB1-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8274BB1-AS1R is usually 5 days.
3.What payment methods are accepted for SI8274BB1-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8274BB1-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8274BB1-AS1R?
SI8274BB1-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8274BB1-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8274BB1-AS1R?
For technical support, including SI8274BB1-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8274BB1-AS1R requirements.
6.How does Aetrix verify that SI8274BB1-AS1R is sourced from the original manufacturer or authorized distributors?
All SI8274BB1-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8274BB1-AS1R meets industry standards.
7.What is the process for return or replacement of SI8274BB1-AS1R?
All SI8274BB1-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI8274BB1-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8274BB1-AS1R part is unused and in its original packaging.
Return procedure for SI8274BB1-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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