Skyworks Solutions Inc. SI8274GB4D-AS1R
- Part No.:
- SI8274GB4D-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI8274GB4D-AS1R.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,486
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Product details
Overview
SI8274GB4D-AS1R from Skyworks Solutions is a dual-channel isolated PWM gate driver with high-side/low-side configuration, 4 A peak output current per channel, 60 ns max propagation delay, and programmable dead-time control via external resistor. It drives SiC/GaN MOSFETs and IGBTs in half-bridge topologies for solar inverters and traction inverters.
For engineers reviewing the SI8274GB4D-AS1R datasheet, SI8274GB4D-AS1R pinout, SI8274GB4D-AS1R application, or SI8274GB4D-AS1R equivalent, key selection criteria include its 200 kV/µs CMTI, separate VOA/VOB outputs with independent supply rails (VDDA/VDDB), TTL-compatible PWM input with >400 mV hysteresis, and automotive-grade AEC-Q100 qualification.
Technical Context
The SI8274GB4D-AS1R implements RF-based silicon isolation with a 2.5 kVRMS UL1577 withstand voltage and supports independent ground referencing for input (GNDI) and dual output sides (GNDA/GNDB). Its architecture includes dedicated UVLO monitoring per supply rail (VDDI, VDDA, VDDB) and internal overlap protection enforced by PWM polarity inversion-VOA high/VOB low on PWM high, and vice versa.
Dead-time is programmable from 10–700 ns using an external resistor (6–100 kΩ) connected to the DT pin, with internal deglitching (15 ns typical) enhancing noise immunity. The device operates across –40 °C to +125 °C and features separate pull-up/pull-down output stages enabling precise slew rate control of power switches.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | 4.0 A per channel - sufficient to directly drive high-gate-charge SiC FETs without external buffers |
| Propagation Delay | 60 ns max - enables high-frequency switching up to 2 MHz with tight timing control |
| CMTI | 200 kV/µs - ensures reliable operation in noisy motor drive and inverter environments |
| Supply Range (Input) | 2.5–5.5 V - compatible with 3.3 V and 5 V microcontrollers and FPGA logic |
| Supply Range (Driver) | 4.2–30 V per side - supports 12 V, 15 V, and 24 V gate drive rails independently on A/B channels |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive and industrial ambient conditions |
| Isolation Withstand | 2.5 kVRMS (UL1577) - meets reinforced insulation requirements for functional safety systems |
Pinout & Package
SI8274GB4D-AS1R is housed in a 16-pin SOIC package with wide-body creepage/clearance for reinforced isolation. Pin assignments are defined per Skyworks datasheet revision 206327E, Figure 3 and Table 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PWM | Digital control input | TTL-compatible PWM signal controlling complementary VOA/VOB outputs; >400 mV hysteresis prevents noise-induced switching |
| VDDI | Input-side power supply | 2.5–5.5 V rail powering isolation transmitter and logic interface; monitored by UVLO circuit |
| GNDI | Input-side ground | Reference for PWM, EN, and DT pins; must be isolated from GNDA/GNDB |
| EN | Enable control | Active-high enable; forces both VOA and VOB low when deasserted, independent of PWM state |
| DT | Dead-time programming | Resistor-to-ground sets 10–700 ns dead time; requires 0.1 µF ceramic capacitor for noise immunity |
| VDDA / GNDA | High-side driver supply/ground | 4.2–30 V isolated rail for VOA output stage; GNDA is local reference, not tied to GNDI or GNDB |
| VOA | High-side gate drive output | Pull-up/pull-down output capable of sourcing/sinking 4 A peak; connects to gate of high-side switch (e.g., Q1 in half-bridge) |
| VDDB / GNDB | Low-side driver supply/ground | 4.2–30 V isolated rail for VOB output stage; GNDB is local reference, electrically separated from GNDA |
| VOB | Low-side gate drive output | Complementary to VOA - active-low when VOA is active-high; drives gate of low-side switch (e.g., Q2) |
Key Features
| Feature | Design Value |
|---|---|
| Programmable dead time | 10–700 ns via single external resistor (6–100 kΩ) - eliminates shoot-through risk without MCU firmware overhead |
| Independent dual-supply outputs | VDDA/GNDA and VDDB/GNDB rails - enables asymmetric gate drive voltages (e.g., +15 V/–5 V) and floating high-side operation |
| RF-based silicon isolation | 2.5 kVRMS UL1577 rating with 200 kV/µs CMTI - superior noise immunity vs. optocouplers and capacitive isolators |
| AEC-Q100 Grade 1 qualification | –40 °C to +125 °C operation with automotive PPAP support - suitable for OBC, BMS, and traction inverter designs |
| UVLO per supply domain | Separate UVLO thresholds for VDDI, VDDA, VDDB - prevents partial operation and ensures safe default-low behavior during brownout |
Applications
| Solar Power Inverter | Traction Inverter |
|---|---|
|
Use Scenario: Half-bridge switching in 3-phase DC–AC conversion for photovoltaic string inverters operating at 100 kHz switching frequency. IC Role / Device Role / Timing Role: Isolated PWM gate driver providing complementary, dead-time-controlled VOA/VOB outputs to SiC MOSFETs in high-voltage (1500 V) bridge legs. Use Value: 60 ns propagation delay matching and 200 kV/µs CMTI prevent false triggering during fast dV/dt transients from adjacent phases. |
Use Scenario: Motor phase-leg driving in battery electric vehicle (BEV) traction inverters with 800 V battery architecture. IC Role / Device Role / Timing Role: Dual-channel isolated driver delivering 4 A peak gate current to 1200 V SiC modules while maintaining <100 ns channel-to-channel skew. Use Value: Independent VDDA/VDDB supplies allow optimized gate voltage sequencing (e.g., +18 V turn-on, –5 V turn-off) for reduced switching losses. |
| Onboard Charger (OBC) | Industrial UPS |
|
Use Scenario: Bi-directional AC–DC and DC–AC conversion in automotive OBCs supporting 11 kW charging with GaN HEMTs. IC Role / Device Role / Timing Role: PWM-controlled isolated driver managing synchronous rectification and inverter modes with seamless transition via EN pin control. Use Value: Dedicated EN pin enables rapid system-level fault shutdown (<1 µs response) without software intervention during overcurrent events. |
Use Scenario: High-efficiency double-conversion UPS for data centers requiring >98% efficiency and 20-year service life. IC Role / Device Role / Timing Role: Gate driver for IGBT-based three-level NPC inverters operating at 16 kHz with strict EMI limits. Use Value: 4 A peak output current and low RDS(ON) (2.7 Ω high-side, 1.0 Ω low-side) minimize conduction loss and thermal stress on gate drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated PWM gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8274AB4D-AS1R | Same pinout and function but rated for –40 °C to +125 °C only (non-automotive grade); lacks AEC-Q100 qualification | Not approved for automotive safety-critical systems; suitable for industrial SMPS and UPS where extended temperature is not required | Select SI8274GB4D-AS1R when AEC-Q100 compliance, PPAP documentation, or IMDS reporting is mandatory |
| ADUM4223BRIZ | 2.5 kVRMS isolation, 4 A output, but fixed 100 ns dead time; no DT pin or programmability; uses iCoupler® capacitive isolation | Lacks design flexibility for variable dead-time tuning; lower CMTI (150 kV/µs) limits use in ultra-fast SiC systems | Choose SI8274GB4D-AS1R when adaptive dead-time control, higher CMTI, or automotive qualification is required |
Compared with Si8274AB4D-AS1R and ADUM4223BRIZ, SI8274GB4D-AS1R uniquely combines AEC-Q100 Grade 1 qualification, field-programmable dead time, and 200 kV/µs CMTI - making it the only option qualified for next-generation 800 V BEV traction inverters requiring both safety certification and dynamic timing optimization.
Availability
SI8274GB4D-AS1R is available at Aetrix Electronics and suitable for solar power inverters, traction inverters, onboard chargers, and industrial uninterruptible power supplies requiring stable component supply across automotive and industrial lifecycles.
Supply support for SI8274GB4D-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, isolation, and precision timing technologies.
The Si827x family was designed specifically for high-reliability isolated gate driving in EV powertrain, renewable energy, and industrial motor control - emphasizing robustness, timing accuracy, and safety certification from the silicon level.
FAQ
What is the isolation rating and safety certification status of the SI8274GB4D-AS1R?
The SI8274GB4D-AS1R provides 2.5 kVRMS isolation per UL1577, with VDE 60747-17, CSA 62368-1, and CQC GB4943.1 certifications for basic insulation. It is AEC-Q100 Grade 1 qualified (–40 °C to +125 °C), and its reinforced insulation architecture meets functional safety requirements for automotive and industrial applications. SI8274GB4D-AS1R does not require external isolation components to meet IEC 60747-17 or UL1577 standards.
How is dead time programmed on the SI8274GB4D-AS1R, and what is the valid range?
Dead time on the SI8274GB4D-AS1R is set by connecting a resistor (RDT) between the DT pin and GNDI. Using RDT = 6–100 kΩ yields 10–700 ns dead time, calculated via DT = 2.02 × RDT + 7.77 (for 10–200 ns) or DT = 6.06 × RDT + 3.84 (for 20–700 ns). A 0.1 µF ceramic capacitor must be placed in parallel with RDT near the DT pin for noise immunity. SI8274GB4D-AS1R implements this dead time on all VOA/VOB transitions.
Does the SI8274GB4D-AS1R support independent power supplies for each output channel?
Yes. SI8274GB4D-AS1R supports fully independent driver-side supplies: VDDA/GNDA powers the VOA output stage, and VDDB/GNDB powers the VOB output stage. Each rail accepts 4.2–30 V and has its own UVLO monitor. This allows asymmetric gate drive configurations (e.g., +15 V for turn-on, –5 V for turn-off) and true floating operation in high-side applications - a capability confirmed in Skyworks datasheet section 1.3 and Figure 3.
What is the peak output current capability of the SI8274GB4D-AS1R, and how is it sustained?
The SI8274GB4D-AS1R delivers 4.0 A peak source/sink current per channel (VOA and VOB), measured at VDDx = 15 V with pulse widths under 250 ns. This is enabled by low RDS(ON) values: 2.7 Ω (high-side) and 1.0 Ω (low-side). Sustained current depends on thermal design and PCB copper area; average current is limited by junction temperature (TJ ≤ 150 °C). SI8274GB4D-AS1R maintains full 4 A capability across its full operating temperature range (–40 °C to +125 °C).
How does the SI8274GB4D-AS1R handle undervoltage lockout (UVLO) conditions?
SI8274GB4D-AS1R implements independent UVLO on all three supply domains: VDDI (input), VDDA (VOA side), and VDDB (VOB side). If any supply falls below its UVLO threshold, the corresponding output defaults to low (VOA or VOB) while preserving isolation integrity. During startup, outputs remain low until all supplies exceed UVLO+ and stabilize for tSTART. SI8274GB4D-AS1R's UVLO behavior is defined in datasheet sections 2.5.2 and Table 8, with hysteresis ensuring glitch-free recovery.
SI8274GB4D-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- SI827x
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- RF Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 200kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 105ns, 75ns
- Pulse Width Distortion (Max):
- 47ns
- Rise / Fall Time (Typ):
- 10.5ns, 13.3ns
- Current - Output High, Low:
- 1.8A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 4.2V ~ 30V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UL, VDE
SI8274GB4D-AS1R FAQ
1.How can I place an order for SI8274GB4D-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8274GB4D-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8274GB4D-AS1R reliable?
The price and inventory of SI8274GB4D-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8274GB4D-AS1R is usually 5 days.
3.What payment methods are accepted for SI8274GB4D-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8274GB4D-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8274GB4D-AS1R?
SI8274GB4D-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8274GB4D-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8274GB4D-AS1R?
For technical support, including SI8274GB4D-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8274GB4D-AS1R requirements.
6.How does Aetrix verify that SI8274GB4D-AS1R is sourced from the original manufacturer or authorized distributors?
All SI8274GB4D-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8274GB4D-AS1R meets industry standards.
7.What is the process for return or replacement of SI8274GB4D-AS1R?
All SI8274GB4D-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI8274GB4D-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8274GB4D-AS1R part is unused and in its original packaging.
Return procedure for SI8274GB4D-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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