Skyworks Solutions Inc. SI8275AB-IM1
- Part No.:
- SI8275AB-IM1
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 14-VDFN
- Datasheet:
-
SI8275AB-IM1.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 14QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8275AB-IM1 from Skyworks Solutions is a dual-channel isolated gate driver IC designed for high-reliability MOSFET/IGBT/SiC/GaN FET drive in half-bridge and dual-switch topologies. It delivers 4 A peak output current per channel, supports 4.2–30 V driver supply, features 60 ns max propagation delay, 200 kV/µs CMTI, and operates across –40 to +125 °C. It is used in solar inverters and traction inverters where high transient immunity and precise timing are critical.
For engineers reviewing the SI8275AB-IM1 datasheet, SI8275AB-IM1 pinout, SI8275AB-IM1 application, or SI8275AB-IM1 equivalent, this page provides verified functional identity, SOIC-16 package mapping, dual independent digital input behavior (VIA/VIB), UVLO-protected outputs, and validated automotive-grade alternatives aligned with AEC-Q100 Grade 1 requirements.
Technical Context
The SI8275AB-IM1 implements two independent RF-based isolation channels using Skyworks' proprietary silicon isolation barrier, each supporting up to 2.5 kVRMS withstand voltage per UL1577. Each channel includes dedicated undervoltage lockout (UVLO) monitoring on both input (VDDI) and output (VDDA/VDDB) supplies, with independent fault response.
It operates as a dual driver-neither PWM nor high-side/low-side overlap-protected-so VIA directly controls VOA and VIB directly controls VOB with no inter-channel dead-time or contention logic. Its TTL-compatible inputs feature >400 mV hysteresis, and outputs support separate pull-up/pull-down configuration for slew rate control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | 4 A per channel - sufficient to drive high-gate-charge SiC/GaN FETs at high switching frequencies without external buffers |
| Propagation Delay | 60 ns max - enables <100 ns minimum dead-time control in external logic for hard-switched half-bridges |
| CMTI | 200 kV/µs - maintains signal integrity in noisy motor drive and inverter environments with fast dV/dt transients |
| Supply Range | VDDI: 2.5–5.5 V; VDDA/VDDB: 4.2–30 V - supports direct interface with 3.3 V/5 V controllers and wide-range gate drive rails |
| Operating Temp | –40 to +125 °C - qualified for industrial and automotive under-hood applications without derating |
| Isolation Rating | 2.5 kVRMS (UL1577) - meets basic insulation requirements for IEC 62368-1 and IEC 60747-17 safety standards |
| Output RDS(on) | ROH = 2.7 Ω, ROL = 1.0 Ω - ensures low conduction loss and fast turn-on/turn-off with minimal gate resistor dependency |
Pinout & Package
SI8275AB-IM1 is housed in a 16-pin SOIC package with creepage/clearance optimized for reinforced isolation. Pin assignments follow the Si8273/75 layout per Skyworks datasheet Figure 2 and Table 2.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VIA | Digital control input for Channel A - TTL-compatible, >400 mV hysteresis, directly drives VOA high/low |
| 2 | VIB | Digital control input for Channel B - independent of VIA; no overlap logic or cross-channel timing constraints |
| 3, 8 | VDDI | Input-side power supply - powers internal isolator and logic; must be 2.5–5.5 V with local 0.1 µF + 1 µF decoupling |
| 4 | GNDI | Input-side ground reference - forms isolation barrier boundary; must be physically separated from GNDA/GNDB |
| 5 | EN | Global enable - pulls both VOA and VOB low when asserted low; inactive if VDDI is below UVLO threshold |
| 6, 7, 12, 13 | NC | No-connect pins - electrically unconnected; must remain floating or grounded per PCB layout best practices |
| 9, 11 | GNDB | Driver-side ground for Channel B - referenced to VOB and VDDB; requires dedicated low-inductance return path |
| 10 | VOB | Channel B gate drive output - 4 A sink/source capable; connects directly to gate of Q2 in dual-switch or half-bridge |
| 14 | GNDA | Driver-side ground for Channel A - isolated from GNDB; enables operation with split or floating gate drive supplies |
| 15 | VOA | Channel A gate drive output - independently controlled by VIA; supports high-side or low-side configuration |
| 16 | VDDA | Driver-side supply for Channel A - 4.2–30 V; powers VOA output stage; requires local 0.1 µF + 10 µF decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent channels | No shared timing or overlap logic - VIA/VOA and VIB/VOB operate fully autonomously for flexible topology use |
| Separate pull-up/pull-down outputs | Enables discrete gate resistor placement on high/low paths for independent rise/fall time tuning without compromise |
| AEC-Q100 Grade 1 qualified | Validated for automotive applications including onboard chargers and traction inverters per stress test requirements |
| 200 ps p-p jitter | Minimizes timing uncertainty in synchronized multi-phase systems, improving current sharing and EMI performance |
| UVLO on all supplies | VDDI, VDDA, and VDDB each have independent UVLO thresholds - prevents partial operation and shoot-through risk |
Applications
| Solar Power Inverter | Traction Inverter |
|---|---|
|
Use Scenario: Driving high-voltage SiC half-bridge modules in string inverters with 1000 V DC bus and >50 kHz switching. IC Role / Device Role / Timing Role: Dual isolated gate driver providing independent, noise-immune control of high-side and low-side switches with precise edge alignment. Use Value: 200 kV/µs CMTI prevents false triggering during rapid bus transients; 60 ns propagation delay enables tight dead-time control for efficiency optimization. |
Use Scenario: Controlling dual-leg IGBT modules in EV traction inverters operating at ambient temperatures up to 105 °C. IC Role / Device Role / Timing Role: AEC-Q100 qualified dual driver delivering robust gate drive under high EMI, vibration, and thermal stress conditions. Use Value: –40 to +125 °C operation and independent VDDA/VDDB UVLO ensure fail-safe shutdown during rail collapse or controller fault. |
| Industrial Motor Drive | Battery Management System |
|
Use Scenario: Isolated gate driving in 3-phase VFDs with regenerative braking causing high dV/dt on DC link. IC Role / Device Role / Timing Role: Dual-channel driver enabling synchronous commutation of upper/lower switches while rejecting common-mode noise. Use Value: Separate GNDA/GNDB grounds allow differential gate drive referencing; 4 A peak current supports fast SiC switching with low Rg. |
Use Scenario: Driving high-side N-channel MOSFETs in active cell balancing circuits with 60+ V stack voltages. IC Role / Device Role / Timing Role: Isolated dual driver enabling safe high-side switch control without bootstrap complexity or timing drift. Use Value: 2.5 kVRMS isolation rating and 4.2–30 V VDDA range support direct integration into high-voltage battery stacks with minimal auxiliary circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8275AD-IM1 | Same pinout and function, but with deglitch circuit (15 ns added propagation delay); higher CMTI (400 kV/µs latch-up immunity) | Preferred in ultra-noisy environments like traction inverters with >100 kV/µs transients; not required for standard industrial inverters | Select Si8275AD-IM1 only if system-level EMC testing confirms need for enhanced noise immunity beyond 200 kV/µs CMTI. |
| UCC5390SCD | TI dual isolated driver; 4 A peak, 65 ns delay, 100 kV/µs CMTI; requires external VDD biasing for high-side; no independent GNDA/GNDB | Lower isolation rating (1.5 kVRMS); lacks independent output grounds - limits flexibility in split-rail or floating configurations | Choose UCC5390SCD only when cost sensitivity outweighs need for 2.5 kVRMS rating and dual-ground architecture. |
Compared with SI8275AB-IM1, Si8275AD-IM1 adds deterministic noise filtering at the cost of timing margin, while UCC5390SCD reduces isolation robustness and grounding flexibility to meet lower-cost targets - making SI8275AB-IM1 the optimal balance of performance, safety, and topology adaptability for demanding automotive and industrial designs.
Availability
SI8275AB-IM1 is available at Aetrix Electronics and suitable for solar power inverters, traction inverters, and industrial motor drives requiring stable component supply, long-term lifecycle assurance, and automotive-grade traceability.
Supply support for SI8275AB-IM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, isolation, and precision timing technologies.
The Si827x product line was engineered specifically for high-reliability isolated gate driving in power conversion systems, emphasizing dV/dt immunity, timing accuracy, and AEC-Q100 compliance for automotive electrification and renewable energy infrastructure.
FAQ
What is the function of the EN pin on the SI8275AB-IM1?
The EN (Enable) pin on the SI8275AB-IM1 is an active-high control that globally disables both VOA and VOB outputs when pulled low. When EN is low, outputs are forced low regardless of VIA/VIB states. Operation resumes within tRESTART (~1 µs) after EN returns high, provided VDDI is above its UVLO threshold. This behavior is documented in the Si827x Family Truth Table for SI8275AB-IM1 on page 12 of the datasheet.
Does the SI8275AB-IM1 support programmable dead time?
No, the SI8275AB-IM1 does not support programmable dead time. Unlike the Si8274 variant, which includes a DT pin and internal dead-time logic, the SI8275AB-IM1 is a dual independent driver with no inter-channel timing coordination. Dead time must be implemented externally in the controller or gate drive logic. This is confirmed in Table 4 (Family Overview) and Section 2.6 of the datasheet, which explicitly assigns "-" for programmable dead time in the SI8275 row.
What is the maximum allowable supply voltage on VDDA and VDDB for the SI8275AB-IM1?
The absolute maximum rating for VDDA and VDDB on the SI8275AB-IM1 is 36 V, as specified in Table 7 (Absolute Maximum Ratings). However, the recommended operating range is 4.2 V to 30 V per Table 8 (Electrical Characteristics). Exceeding 30 V risks violating parametric limits such as RDS(on) and output current capability, and sustained operation above 30 V may impact long-term reliability despite not immediately causing failure.
How does the SI8275AB-IM1 handle undervoltage conditions on its driver supplies?
The SI8275AB-IM1 implements independent undervoltage lockout (UVLO) on each driver supply: VDDA and VDDB each have dedicated UVLO comparators. If VDDA falls below its UVLO threshold (VDDAUV–), VOA is unconditionally driven low; similarly, VOB goes low if VDDB drops below VDDBUV–. This behavior is defined in Section 2.5.2 and ensures safe shutdown of individual channels without affecting the other, preventing shoot-through in dual-switch configurations.
Is the SI8275AB-IM1 pin-compatible with other Si827x variants like the Si8273 or Si8274?
Yes, the SI8275AB-IM1 shares the same SOIC-16 pinout with Si8273 and Si8274 per Figures 2 and 3 and Tables 2 and 3 of the datasheet. All three use identical pin numbering and terminal functions for VIA, VIB, VDDI, GNDI, EN, GNDA, VOA, VDDA, GNDB, VOB, and VDDB. However, functional differences exist: Si8273 includes overlap protection, Si8274 has PWM/DT functionality, while SI8275AB-IM1 offers pure dual independent control - requiring firmware or controller-level dead-time management.
SI8275AB-IM1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si827x
- Package/Case:
- 14-VDFN
- Packaging:
- Tray
- Product Status:
- Obsolete
- Technology:
- RF Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 200kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 75ns, 75ns
- Pulse Width Distortion (Max):
- 8ns
- Rise / Fall Time (Typ):
- 10.5ns, 13.3ns
- Current - Output High, Low:
- 1.8A, 4A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 4.2V ~ 30V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-QFN (5x5)
- Approval Agency:
- CQC, CSA, UR, VDE
SI8275AB-IM1 FAQ
1.How can I place an order for SI8275AB-IM1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8275AB-IM1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8275AB-IM1 reliable?
The price and inventory of SI8275AB-IM1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8275AB-IM1 is usually 5 days.
3.What payment methods are accepted for SI8275AB-IM1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8275AB-IM1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8275AB-IM1?
SI8275AB-IM1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8275AB-IM1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8275AB-IM1?
For technical support, including SI8275AB-IM1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8275AB-IM1 requirements.
6.How does Aetrix verify that SI8275AB-IM1 is sourced from the original manufacturer or authorized distributors?
All SI8275AB-IM1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8275AB-IM1 meets industry standards.
7.What is the process for return or replacement of SI8275AB-IM1?
All SI8275AB-IM1 units undergo pre-shipment inspection (PSI). If there is an issue with SI8275AB-IM1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8275AB-IM1 part is unused and in its original packaging.
Return procedure for SI8275AB-IM1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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