Skyworks Solutions Inc. SI8275DAD-IM1R

Overview

SI8275DAD-IM1R from Skyworks Solutions is a dual-channel isolated gate driver IC designed for high-reliability MOSFET/IGBT/SiC/GaN half-bridge and dual-switch applications. It delivers 4 A peak output current per channel, supports 2.5 kVRMS isolation (UL1577), achieves ≤60 ns max propagation delay, and operates across –40 to +125 °C with input supply range 2.5–5.5 V and driver supply range 4.2–30 V. It is used in solar inverters and traction inverters where high dV/dt immunity and precise timing control are critical.

For engineers reviewing the SI8275DAD-IM1R datasheet, SI8275DAD-IM1R pinout, SI8275DAD-IM1R application, or SI8275DAD-IM1R equivalent, this page provides verified technical context, validated pin functions, confirmed dual-driver timing behavior, real-world automotive and industrial use cases, and two rigorously cross-checked alternative parts with documented functional and packaging differences.

Technical Context

The SI8275DAD-IM1R implements two independent isolated gate drive channels using Skyworks' proprietary RF-based silicon isolation barrier, enabling 200 kV/µs common-mode transient immunity (CMTI) and eliminating optocoupler aging. Each channel features TTL-compatible digital inputs (VIA/VIB), dedicated enable (EN), separate high-side (VOA/VOB) and low-side (GNDA/GNDB) ground references, and independent UVLO monitoring on both input and output supplies.

Unlike Si8273 (high-side/low-side with overlap protection) or Si8274 (PWM-input with programmable dead time), the SI8275DAD-IM1R operates as a true dual driver: both outputs respond directly and independently to their respective inputs without inherent overlap logic or dead-time circuitry. Its SOIC-16 package supports galvanic isolation between input and each output domain, with no internal connection between GNDA and GNDB.

Key Specifications

Pinout & Package

SI8275DAD-IM1R is housed in a 16-pin SOIC package with creepage/clearance optimized for reinforced isolation. Pin assignments follow the Si8273/75 layout per Skyworks datasheet Figure 2 and Table 2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual isolated gate driver applications.

Compared with Si8275BD-IM1R, SI8275DAD-IM1R offers identical functionality at lower cost and standard temperature grade, while UCC5390SCDR sacrifices CMTI headroom and ground isolation flexibility for tighter integration with TI controller families.

Availability

SI8275DAD-IM1R is available at Aetrix Electronics and suitable for solar power inverters, traction inverters, and industrial motor drives requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.

Supply support for SI8275DAD-IM1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance power systems.

The Si827x product line was engineered specifically for robust isolated gate driving in high-voltage, high-frequency power conversion - targeting automotive traction, renewable energy, and industrial motor control where optocoupler limitations in speed, reliability, and CMTI are unacceptable.

FAQ

What is the maximum allowable dV/dt transient the SI8275DAD-IM1R can withstand without malfunction?

The SI8275DAD-IM1R guarantees 200 kV/µs common-mode transient immunity (CMTI) per datasheet Table 8. This means it maintains correct logic state and output behavior even when subjected to rapid voltage changes across its isolation barrier - such as those occurring during SiC switch turn-off in 800 V systems. This performance is achieved via Skyworks' RF-based silicon isolation, not optical coupling, and is validated across –40 to +125 °C.

Does the SI8275DAD-IM1R support high-side gate driving without a bootstrap circuit?

Yes. The SI8275DAD-IM1R supports true high-side driving because its VOA and VOB outputs are fully isolated and referenced to independent grounds (GNDA and GNDB). When VDDA is supplied relative to GNDA, VOA can directly drive the gate of a high-side switch whose source is at a floating potential - eliminating need for bootstrap diodes or capacitors in topologies like active clamp flyback or isolated half-bridge. This is confirmed in Figure 24 and Section 3.1.2 of the datasheet.

What happens to the outputs of the SI8275DAD-IM1R during input supply undervoltage?

When VDDI falls below its UVLO threshold (VDDIUV– ≈ 2.1 V), the SI8275DAD-IM1R forces both VOA and VOB into a low-output state regardless of VIA/VIB states, as specified in Section 2.5.2. This fail-safe behavior prevents partial gate drive that could cause shoot-through. Outputs remain low until VDDI rises above VDDIUV+ (≈ 2.3 V) and tSTART delay elapses - ensuring clean startup sequencing. This is distinct from output-side UVLO, which acts independently on VDDA/VDDB.

Can the SI8275DAD-IM1R replace the Si8273 in a high-side/low-side configuration?

No - the SI8275DAD-IM1R lacks built-in overlap protection and cannot safely replace the Si8273 in a single high-side/low-side pair without external logic. The Si8273 enforces mutual exclusion (VOA and VOB never high simultaneously), while the SI8275DAD-IM1R allows simultaneous high outputs. To use SI8275DAD-IM1R in half-bridge mode, external dead-time generation (e.g., FPGA or MCU) and careful PCB layout to prevent shoot-through are mandatory - per truth table behavior in Table 5.

What is the purpose of the NC pins (6, 7, 12, 13) on the SI8275DAD-IM1R SOIC-16 package?

Pins 6, 7, 12, and 13 are designated No Connect (NC) in the SI8275DAD-IM1R datasheet Table 2 and must remain unconnected on the PCB. These pins serve no electrical function and are left floating to maintain isolation barrier integrity and creepage distance. Soldering or routing traces to them violates Skyworks' layout guidance and risks compromising 2.5 kVRMS withstand voltage or CMTI performance - confirmed in Section 3.3.1 and Figure 2.