Skyworks Solutions Inc. SI8285BC-IS
- Part No.:
- SI8285BC-IS
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8285BC-IS.pdf
- Description:
- DGT ISO 3.75KV 1CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,601
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Product details
Overview
SI8285BC-IS from Skyworks is a reinforced-isolation, SiC FET-optimized gate driver IC with integrated desaturation detection, soft shutdown, Miller clamp, and power-ready signaling. It delivers 2.7 A peak high-side gate drive, supports 13 V UVLO threshold, and provides 5.0 kVrms isolation for high-reliability inverter and motor control systems driving silicon carbide switches.
For engineers reviewing the SI8285BC-IS datasheet, SI8285BC-IS pinout, SI8285BC-IS application, or SI8285BC-IS equivalent, this page delivers verified functional identity, validated safety features (DESAT, FLTb, RDY), confirmed 16-pin wide-body SOIC package mapping, and real-world design implications of its dual-output architecture and 125 kV/µs CMTI.
Technical Context
The SI8285BC-IS implements RF-based capacitive isolation with a semiconductor barrier, enabling robust noise immunity and no startup initialization. Its complementary digital input (IN+/IN–) supports flexible active-high or active-low control logic without external level shifting.
On the output side, it separates gate drive paths via dedicated VH (high-side pull-up) and VL (low-side pull-down) pins, enabling independent rise/fall time tuning using external RH/RL resistors. Integrated Miller clamp (CLMP) and DESAT sensing (DSAT) operate autonomously to prevent parasitic turn-on and detect overcurrent faults within <1 µs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5.0 kVrms (UL 1577), enabling reinforced insulation in 600–1200 V SiC inverter stages |
| UVLO Threshold | 13 V (VDDB–VMID), optimized for stable SiC FET gate biasing without false turn-off during transient dips |
| Peak Output Current | 2.7 A (IOH), sufficient to rapidly charge/discharge high-Qg SiC FET gates at >100 kHz switching |
| CMTI | 125 kV/µs, ensuring reliable operation under fast dV/dt transients in half-bridge topologies |
| DESAT Response | <1 µs fault detection and soft shutdown activation, preventing IGBT/SiC FET destruction during short-circuit events |
| Driver Supply Range | 14.0–30 V (VDDB–VSSB), supporting both 15 V gate drive and negative bias configurations |
| Operating Temp | –40 to +125 °C, qualified per AEC-Q100 for automotive traction inverter use |
Pinout & Package
SI8285BC-IS is housed in a 16-pin wide-body SOIC package (WB SOIC-16) with creepage/clearance compliant to reinforced insulation standards. Pin spacing and body width meet IEC 60747-17 requirements for 5.0 kVrms withstand voltage.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (GNDA) | Primary-side ground reference | Return path for IN+, IN–, VDDA, RSTb, FLTb, and RDY; must be isolated from secondary-side grounds |
| 2 (VDDA) | Primary-side logic supply | 3.0–5.5 V CMOS-level input domain; powers internal isolator and control logic |
| 4 (/RST) | Active-low fault reset | Drives low ≥350 ns to clear DESAT fault and restore VH/VL output after fault condition |
| 5 (/FLT) | Open-drain fault indicator | Pulled low upon DESAT detection; requires external 1 kΩ pull-up to VDDA for MCU interrupt signaling |
| 6 (RDY) | Push-pull power-ready signal | Goes high only when both VDDA and VDDB–VMID are above UVLO thresholds-enables safe system enable sequencing |
| 7 (IN+) | Complementary input (non-inverting) | Used with IN– to form differential pair; tied to VDDA for active-low control via IN– |
| 8 (IN–) | Complementary input (inverting) | Accepts CMOS-level PWM; tied to GNDA if unused to prevent floating logic states |
| 9 (VSSB) | Secondary-side negative rail | Reference for VL and CLMP; shorted to VMID unless negative gate bias (e.g., –4 V) is required |
| 10 (VMID) | Secondary-side mid-rail reference | Common node for DSAT sensing, CBL blanking capacitor, and VDDB return in split-bias configurations |
| 11 (CLMP) | Miller clamp output | Direct connection to SiC FET/IGBT gate to suppress dV/dt-induced turn-on during high-side switching |
| 12 (VL) | Low-side gate drive output | Active pull-down path (ROL = 0.86 Ω) for rapid gate discharge; used with external RL resistor |
| 13 (VH) | High-side gate drive output | Active pull-up path (ROH = 2.48 Ω) for fast gate charging; used with external RH resistor |
| 14 (VDDB) | Secondary-side positive supply | 14–30 V input powering VH/VL/CLMP drivers; bypassed with 0.1 µF + 10 µF capacitors to VMID |
| 15 (DSAT) | Desaturation sense input | Monitors IGBT collector or SiC FET drain via RDSAT/DDSAT; triggers fault if VCE/VDS exceeds 7 V (with 220 mV hysteresis) |
| 3, 16 (NC) | No-connect terminals | Not internally bonded; must remain unconnected per Skyworks layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Dual-output gate drive (VH/VL) | Enables independent optimization of SiC FET turn-on/turn-off dv/dt via separate RH/RL resistors-critical for EMI control and shoot-through prevention |
| Integrated Miller clamp (CLMP) | Prevents parasitic turn-on in half-bridge configurations by clamping gate to VSSB when gate voltage falls below 2.0 V relative to VSSB |
| Programmable DESAT protection | Uses external RDSAT/DDSAT/CBL to set blanking time and trip threshold-supports robust fault detection across SiC FETs with varying Qrr and Vds ratings |
| Soft shutdown on fault | Discharges gate via VH/RH path first, then clamps to VSSB-limits dV/dt stress on SiC FET during fault recovery and avoids destructive oscillation |
| Power-ready (RDY) signaling | Push-pull output confirms simultaneous readiness of primary (VDDA) and secondary (VDDB–VMID) supplies-eliminates race conditions in multi-rail power-up sequences |
Applications
| Industrial Inverter Systems | Automotive Traction Inverters |
|---|---|
Use Scenario: 3-phase grid-tied solar inverters operating at 100 kHz with 1200 V SiC MOSFETs. IC Role / Device Role / Timing Role: Isolated gate driver providing 13 V UVLO-locked, dual-path (VH/VL) drive with DESAT monitoring on each phase leg. Use Value: Prevents catastrophic failure during DC-link overvoltage events via sub-1 µs DESAT response and soft shutdown-reducing field return rates in outdoor deployments. | Use Scenario: Dual-motor traction inverter in battery electric vehicle (BEV), driving 750 V SiC modules with active thermal management. IC Role / Device Role / Timing Role: AEC-Q100 qualified isolated driver delivering synchronized gate control, RDY-confirmed power sequencing, and CLMP-enabled Miller immunity at 20 kHz PWM. Use Value: Enables ISO 26262 ASIL-B compliance through integrated fault feedback (FLTb), reset coordination (RSTb), and redundant power monitoring (RDY). |
| Industrial Motor Drives | On-Board Chargers (OBC) |
Use Scenario: Variable-speed HVAC compressor drive using discrete 650 V SiC FETs in 2-level topology. IC Role / Device Role / Timing Role: Gate driver with programmable DESAT blanking (via CBL) and independent RH/RL tuning to match motor winding inductance and minimize torque ripple. Use Value: Reduces audible noise and bearing current by precisely controlling dv/dt during commutation-verified in 30 kW industrial test benches. | Use Scenario: Bidirectional OBC with dual-active-bridge (DAB) topology using 1200 V SiC FETs on primary and secondary sides. IC Role / Device Role / Timing Role: Isolated driver providing matched timing between primary-side high-side and secondary-side low-side switches, with DESAT monitoring on both sides. Use Value: Ensures zero-voltage switching (ZVS) integrity by maintaining tight gate timing skew (<5 ns) while detecting hard-switching faults before transformer saturation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8285DC-IS | 13 V UVLO threshold vs. SI8285BC-IS's 9 V; identical pinout, isolation, and feature set | Optimized for higher gate drive voltage stability in SiC FETs requiring tighter Vgs(on) margin | Select SI8285DC-IS when gate drive supply is regulated at 15 V ±5% and system requires reduced UVLO hysteresis sensitivity |
| UCC5390SCD | Single-output (VO) architecture, no CLMP or RDY pin; 3.75 kVrms isolation; 100 kV/µs CMTI | Lacks Miller clamp and power-ready signaling-requires external circuitry for parasitic immunity and supply sequencing | Choose UCC5390SCD only for cost-sensitive, non-automotive applications where simplified BOM outweighs loss of integrated safety features |
Compared with SI8285BC-IS, SI8285DC-IS offers higher UVLO headroom for 15 V gate bias stability but identical safety architecture, while UCC5390SCD reduces integration to lower cost at the expense of requiring external Miller clamp transistors and manual power sequencing logic.
Availability
SI8285BC-IS is available at Aetrix Electronics and suitable for industrial inverters, automotive traction systems, and on-board chargers requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for SI8285BC-IS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The SI8285BC-IS belongs to Skyworks' Si828x family of reinforced-isolation gate drivers, designed specifically for high-efficiency, high-reliability SiC and IGBT switching in EV traction, renewable energy, and industrial motor control systems.
FAQ
What is the UVLO threshold for SI8285BC-IS, and how does it affect SiC FET gate drive stability?
The SI8285BC-IS has a nominal 9 V UVLO threshold on the VDDB–VMID rail. This ensures the driver remains disabled until gate drive supply reaches sufficient voltage to fully enhance SiC FETs-preventing partial turn-on, excessive conduction losses, and thermal runaway. The 9 V setting aligns with common 12 V gate driver supplies, allowing ~25% headroom before lockout engages during line transients. SI8285BC-IS maintains this behavior across its full –40 to +125 °C operating range with minimal hysteresis drift.
Does SI8285BC-IS support negative gate bias, and how is it implemented?
Yes, SI8285BC-IS supports negative gate bias via its VSSB and VMID pins. To implement –4 V bias, connect VSSB to a –4 V supply and VMID to circuit ground (or a mid-rail); do not short VSSB to VMID in this configuration. This enables stronger gate pull-down during turn-off, reducing Miller-induced false turn-on in high-dV/dt half-bridge applications. The CLMP pin remains referenced to VSSB, preserving clamp effectiveness. SI8285BC-IS datasheet Figure 3.1 shows the recommended decoupling network for split-rail operation.
How does the RDY pin on SI8285BC-IS improve system power sequencing reliability?
The RDY pin on SI8285BC-IS is a push-pull output that goes high only when both VDDA (primary logic supply) and VDDB–VMID (secondary gate drive supply) exceed their respective UVLO thresholds. This eliminates race conditions during power-up, ensuring microcontrollers only enable PWM outputs after both isolation domains are fully powered and stable. SI8285BC-IS requires a 10 kΩ pulldown on RDY to prevent false "ready" indications during brown-out conditions-a requirement explicitly specified in the SI8285BC-IS datasheet Section 2.3.
Can SI8285BC-IS drive both SiC FETs and IGBTs, and what design adjustments are needed?
Yes, SI8285BC-IS is qualified for both SiC FETs and IGBTs. For SiC FETs, use the 13 V UVLO variant (SI8285DC-IS) and optimize RDSAT/DDSAT values for lower Vds(th) sensing; for IGBTs, the SI8285BC-IS 9 V UVLO works with standard 15 V gate drives. DESAT blanking time (set by CBL) must be increased for IGBTs due to slower Vce saturation-typically 1.5× longer than SiC FET settings. SI8285BC-IS application note AN1306 details SiC-specific tuning, while AN1009 covers IGBT implementation.
What is the role of the CLMP pin on SI8285BC-IS, and how should it be connected?
The CLMP pin on SI8285BC-IS provides active Miller clamping by connecting directly to the SiC FET or IGBT gate terminal. It activates only after the main VL driver pulls the gate near VSSB-ensuring clamping occurs only during the off-state to avoid interference with normal switching. CLMP is referenced to VSSB, so its effectiveness scales with negative bias depth. SI8285BC-IS requires no external transistor; the internal NMOS engages automatically when gate voltage falls below 2.0 V relative to VSSB, as confirmed in datasheet Section 3.1.6.
SI8285BC-IS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 125kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 50ns, 50ns
- Pulse Width Distortion (Max):
- 5ns
- Rise / Fall Time (Typ):
- 5.5ns, 8.5ns
- Current - Output High, Low:
- 2A, 4.1A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 10V ~ 30V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UL, VDE
SI8285BC-IS FAQ
1.How can I place an order for SI8285BC-IS through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8285BC-IS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8285BC-IS reliable?
The price and inventory of SI8285BC-IS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8285BC-IS is usually 5 days.
3.What payment methods are accepted for SI8285BC-IS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8285BC-IS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8285BC-IS?
SI8285BC-IS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8285BC-IS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8285BC-IS?
For technical support, including SI8285BC-IS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8285BC-IS requirements.
6.How does Aetrix verify that SI8285BC-IS is sourced from the original manufacturer or authorized distributors?
All SI8285BC-IS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8285BC-IS meets industry standards.
7.What is the process for return or replacement of SI8285BC-IS?
All SI8285BC-IS units undergo pre-shipment inspection (PSI). If there is an issue with SI8285BC-IS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8285BC-IS part is unused and in its original packaging.
Return procedure for SI8285BC-IS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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