Skyworks Solutions Inc. SI8285BC-ISR

Overview

SI8285BC-ISR from Skyworks is a reinforced-isolation, SiC FET–optimized gate driver IC with integrated desaturation detection, soft shutdown, Miller clamp, and power-ready signaling. It delivers 2.7 A peak high-side output current, supports 30 V driver supply, features 5.0 kV_rms isolation (UL 1577), and operates across –40 to +125 °C for traction inverter and industrial inverter applications.

For engineers reviewing the SI8285BC-ISR datasheet, SI8285BC-ISR pinout, SI8285BC-ISR application, or SI8285BC-ISR equivalent, this page provides verified functional identity, validated pin roles, confirmed safety features (DESAT, FLTb, RDY, CLMP), exact UVLO threshold (13 V), and real-world layout-critical design meanings for VH/VL/DSAT/RDY pins - all aligned to Skyworks Rev. 2.0 datasheet and SOIC-16 wide-body package constraints.

Technical Context

The SI8285BC-ISR implements RF-based capacitive isolation with 125 kV/µs CMTI, enabling robust noise immunity in high-dV/dt SiC switching environments. Its dual-output architecture separates VH (high-side pull-up) and VL (low-side pull-down) paths, allowing independent gate resistor tuning for precise control of SiC FET V_DS rise/fall times.

It integrates a dedicated DSAT pin with 7 V nominal desaturation threshold and 220 mV hysteresis, coupled with an internal blanking timer driven by external C_BL. The Miller clamp (CLMP pin) activates only after gate voltage falls below 2.0 V relative to VSSB, preventing interference during active switching while securing off-state integrity against parasitic turn-on.

Key Specifications

Pinout & Package

SI8285BC-ISR uses a 16-pin wide-body SOIC package (WB SOIC-16) with 1.27 mm pitch, 10.3 mm body width, and creepage ≥8.3 mm - compliant with reinforced insulation per IEC 62368-1 and UL 1577.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated gate driver applications.

Compared with SI8285BD-ISR, SI8285BC-ISR offers identical SiC-optimized features (DESAT, RDY, CLMP, soft shutdown) but trades 1.25 kV_rms isolation margin for lower cost and broader availability in industrial-grade supply chains; versus UCC5390SCDR, it delivers superior SiC-specific protection and timing control at the expense of pin-count and layout complexity.

Availability

SI8285BC-ISR is available at Aetrix Electronics and suitable for industrial inverters, EV traction systems, on-board chargers, and isolated DC-DC converters requiring stable component supply across extended temperature and high-reliability automotive programs.

Supply support for SI8285BC-ISR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance power systems.

The SI8285 family is part of Skyworks' ISODriver™ portfolio, engineered specifically for wide-bandgap power switching - delivering integrated safety, precision timing, and reinforced isolation to enable next-generation SiC and GaN-based motor drives and energy conversion systems.

FAQ

What is the UVLO threshold for SI8285BC-ISR and how does it impact SiC FET operation?

The SI8285BC-ISR has a fixed 13 V undervoltage lockout (UVLO) threshold referenced between VDDB and VMID. This matches the minimum gate drive voltage required to fully enhance commercial 1200 V SiC FETs while avoiding partial turn-on that causes excessive conduction loss and thermal runaway. When VDDB falls below 13 V, the SI8285BC-ISR forces VL low and disables VH, ensuring the SiC FET remains safely off until stable gate drive is restored - a critical safeguard during bus voltage sag in EV traction inverters.

How does the RDY pin on SI8285BC-ISR improve system reliability compared to polling-based readiness checks?

Unlike software-based readiness verification, the RDY pin on SI8285BC-ISR is a hardware push-pull signal that goes high only when both VDDA and VDDB have exited their respective UVLO states - confirming stable logic and gate drive power simultaneously. This eliminates race conditions where MCU firmware might enable PWM before VDDB is fully regulated, preventing unintended switch turn-on. A 10 kΩ pulldown on RDY further prevents false assertions during cold start, making SI8285BC-ISR suitable for ASIL-B–compliant automotive systems without additional supervision circuitry.

Can SI8285BC-ISR drive both SiC FETs and IGBTs, and what design adjustments are needed?

Yes, SI8285BC-ISR is qualified for both SiC FETs and IGBTs, as confirmed in Skyworks' Applications Information section. For SiC FETs, use VSSB = VMID (0 V bias) or VSSB = –4 V (negative bias) to reduce turn-off losses; for IGBTs, VSSB = VMID is standard. The DSAT circuit requires different R_DSAT values: 10 Ω for 1200 V SiC FETs (to maintain 7 V threshold at V_DS = 1000 V) versus 22 Ω for 1700 V IGBTs. Layout must place R_DSAT/D_DSAT within 5 mm of the switch collector/drain to preserve DESAT accuracy in both cases.

What is the function of the CLMP pin on SI8285BC-ISR and why is it absent on SI8286 variants?

The CLMP pin on SI8285BC-ISR provides a dedicated Miller clamp output that actively pulls the SiC FET or IGBT gate to VSSB when gate voltage falls below 2.0 V - preventing parasitic turn-on during high-dV/dt commutation. This feature is exclusive to SI8285 devices because their separate VH/VL architecture allows independent control of main drive and clamp functions. SI8286 uses a single VO pin, making integrated clamping incompatible with its output stage design; users must add external clamp transistors if Miller protection is required with SI8286.

How does the soft shutdown feature in SI8285BC-ISR differ from hard shutdown, and when is each appropriate?

Soft shutdown in SI8285BC-ISR uses the internal 60 Ω RSS impedance to gradually discharge the gate via VH and external R_H, limiting dV/dt to safe levels (<50 V/ns) and preventing EMI-induced shoot-through in adjacent legs. Hard shutdown (not implemented in SI8285BC-ISR) would instantly collapse gate voltage, risking voltage overshoot and oscillation. Soft shutdown is mandatory for SiC FETs due to their fast intrinsic diode recovery and low gate charge; it is activated automatically on DESAT detection and cannot be disabled - ensuring fail-safe behavior in SI8285BC-ISR.