Skyworks Solutions Inc. SI8285BD-IS
- Part No.:
- SI8285BD-IS
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8285BD-IS.pdf
- Description:
- DGTL ISO 5KV 1CH GATE DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,220
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Product details
Overview
SI8285BD-IS from Skyworks is a reinforced-isolation, SiC FET-optimized gate driver IC with integrated desaturation detection, soft shutdown, Miller clamp, and power-ready signaling. It delivers 2.7 A peak high-side gate drive, supports 30 V driver supply, features 5.0 kVrms isolation (UL1577), and operates across –40 to +125 °C for traction inverters and industrial SiC-based motor drives.
For engineers reviewing the SI8285BD-IS datasheet, SI8285BD-IS pinout, SI8285BD-IS application, or SI8285BD-IS equivalent, this page provides verified functional identity, validated safety features (DESAT, UVLO, FLTb/RDY), confirmed 16-pin wide-body SOIC package mapping, and real-world design implications for SiC FET gate control in high-dV/dt environments.
Technical Context
The SI8285BD-IS implements RF-based capacitive isolation with 125 kV/µs CMTI, enabling robust noise immunity in fast-switching SiC systems. Its dual-output architecture (VH/VL) allows independent gate rise/fall time tuning via external RH/RL resistors - critical for optimizing switching losses and EMI in half-bridge topologies.
It integrates a dedicated DSAT pin with 7 V threshold and 220 mV hysteresis, coupled with programmable blanking via external CBL capacitor, to detect IGBT/SiC FET desaturation within <1 µs. The Miller clamp (CLMP) engages only after gate voltage falls below 2.0 V relative to VSSB, preventing interference during active switching while securing off-state integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5.0 kVrms (UL1577, 1 min) - enables reinforced insulation in 1000 VDC+ DC-link systems |
| Driver Supply Range | 10–30 V (VDDB–VSSB) - supports 13 V UVLO threshold for SiC FET gate bias stability |
| Peak Output Current | 2.7 A (IOH, typ.) - sufficient to rapidly charge/discharge SiC FET gates up to 100 nC |
| Common-Mode Transient Immunity | 125 kV/µs - prevents false triggering during >50 V/ns dV/dt transients in SiC inverters |
| Desat Detection Threshold | 7 V (nominal), 220 mV hysteresis - accurately identifies VDS >7 V in SiC FETs before thermal runaway |
| Soft Shutdown Impedance | 60 Ω (RSS) - controls gate discharge rate to limit dV/dt during fault recovery |
| UVLO Threshold | 9 V (Si8285BD-IS variant) - ensures gate drive remains disabled until driver rail stabilizes above SiC turn-on threshold |
| Operating Temperature | –40 to +125 °C - qualified for under-hood automotive traction inverter use |
Pinout & Package
Package: 16-pin wide-body SOIC (WB SOIC-16), RoHS-compliant, 260 °C reflow compatible.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (GNDA) | Primary-side ground reference | Return path for input logic and VDDA; must be isolated from secondary-side grounds |
| 2 (VDDA) | Input-side supply | 3.0–5.5 V CMOS-level logic supply; powers internal RF transmitter and control logic |
| 4 (/RST) | Active-low fault reset | Drives low ≥350 ns to clear DESAT fault and restore VH/VL output after shutdown |
| 5 (/FLT) | Open-drain fault indicator | Pulled high externally; goes low on DESAT/UVLO fault; OR-capable with multiple drivers |
| 6 (RDY) | Push-pull ready signal | Goes high only when both VDDA and VDDB exit UVLO - confirms full system power readiness |
| 7 (IN+) | Complementary input (non-inverting) | Used with IN− for differential noise immunity; tied to VDDA for active-low control via IN− |
| 8 (IN−) | Complementary input (inverting) | Accepts CMOS-level signals; tied to GNDA if unused to prevent floating input |
| 10 (VMID) | Midpoint reference for driver outputs | Provides return for DSAT sensing and optional negative gate bias (VSSB < VMID) |
| 11 (CLMP) | Miller clamp output | Directly connects to SiC FET/IGBT gate to sink Miller current and prevent parasitic turn-on |
| 12 (VL) | Low-side gate drive output | Active pull-down path; ROL = 0.86 Ω enables fast gate discharge for SiC FETs |
| 13 (VH) | High-side gate drive output | Active pull-up path; ROH = 2.48 Ω supports 2.7 A peak current into gate capacitance |
| 14 (VDDB) | Secondary-side supply | 10–30 V driver rail; powers VH/VL/CLMP outputs and internal bias circuits |
| 15 (DSAT) | Desaturation sense input | Monitors switch VDS/VCE via external RDSAT/DDSAT; triggers fault if >7 V post-blanking |
| 9, 16 (VSSB, NC) | Secondary-side ground / No connect | VSSB is driver output return; NC pins must remain unconnected per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Miller clamp (CLMP) | Engages only after gate voltage drops below 2.0 V (relative to VSSB), eliminating shoot-through risk without compromising switching speed |
| Programmable DESAT blanking | External CBL capacitor sets blanking time (tBlanking = CBL × 7 V / IChg) to suppress turn-on transients while retaining fast fault response |
| Dual independent gate drive outputs (VH/VL) | Enables asymmetric gate resistor networks (RH/RL) to independently optimize SiC FET dV/dt and di/dt for EMI and reliability trade-offs |
| Power-ready (RDY) signaling | Push-pull RDY pin confirms simultaneous readiness of primary (VDDA) and secondary (VDDB) supplies - eliminates startup race conditions in multi-rail systems |
| Soft shutdown with controlled impedance | 60 Ω internal RSS discharges gate gradually to limit dV/dt during fault, preventing voltage overshoot and device stress |
| SiC-optimized UVLO (9 V) | Prevents partial turn-on of SiC FETs by holding VL low until driver rail exceeds minimum gate bias needed for full enhancement |
Applications
| Industrial Motor Drives | Renewable Energy Inverters |
|---|---|
Use Scenario: Variable-speed AC induction and PMSM motor control in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Isolated gate driver for 1200 V SiC FET half-bridges; provides DESAT protection and soft shutdown during overload or short-circuit events. Use Value: Enables >100 kHz switching with <1 µs fault clearance, reducing thermal stress and extending motor drive lifetime in continuous-duty applications. | Use Scenario: Grid-tied solar string inverters converting DC from photovoltaic arrays to 230 VAC. IC Role / Device Role / Timing Role: High-CMTI gate driver for SiC-based three-phase H-bridge; synchronizes gate timing across phases while rejecting common-mode noise from transformerless topologies. Use Value: 125 kV/µs CMTI prevents false triggering during rapid PV array voltage transients, ensuring grid compliance and system uptime. |
| Traction Inverters (EV/HEV) | On-Board Chargers (OBC) |
Use Scenario: Traction inverter modules controlling permanent magnet motors in battery electric vehicles. IC Role / Device Role / Timing Role: AEC-Q100 qualified isolated driver for 750 V SiC FETs; manages gate timing, DESAT detection, and fault reporting to vehicle MCU via /FLT and RDY pins. Use Value: Integrated Miller clamp and 5.0 kVrms isolation meet ASIL-B functional safety requirements for torque control loops without external components. | Use Scenario: Bidirectional OBCs converting AC grid power to charge EV batteries and feeding regenerative energy back to the grid. IC Role / Device Role / Timing Role: Dual-channel gate driver (per phase) for SiC FETs in totem-pole PFC and DC-DC stages; coordinates soft-start and fault recovery sequences. Use Value: 9 V UVLO and RDY signaling ensure synchronized power-up of PFC and isolation stages, avoiding inrush current faults during cold start. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8285BC-IS | Same pinout and architecture, but 3.75 kVrms isolation rating and 9 V UVLO - lower isolation margin, identical SiC FET support | Approved for industrial inverters with ≤600 VDC bus; not certified for automotive traction systems requiring 5 kVrms | Select SI8285BC-IS only when UL1577 3.75 kVrms suffices and cost optimization is prioritized over automotive qualification. |
| UCC5870QDWJRQ1 | Texas Instruments' AEC-Q100 qualified 5.7 kVrms SiC gate driver with integrated DESAT, but uses single VO output (no VH/VL separation) and lacks CLMP pin | Requires external Miller clamp circuitry; supports higher 35 V driver supply but offers no independent rise/fall control without added diodes | Choose UCC5870QDWJRQ1 when system-level BOM count reduction outweighs need for native Miller clamping and asymmetric gate drive tuning. |
Compared with SI8285BC-IS, the SI8285BD-IS provides higher isolation (5.0 vs. 3.75 kVrms) for enhanced safety in 1000 VDC+ traction systems; versus UCC5870QDWJRQ1, it delivers native VH/VL outputs and integrated CLMP - reducing external component count and improving SiC FET reliability in high-dV/dt motor drives.
Availability
SI8285BD-IS is available at Aetrix Electronics and suitable for traction inverters, industrial SiC motor drives, and renewable energy grid-tie inverters requiring stable component supply, automotive-grade traceability, and long-term lifecycle support.
Supply support for SI8285BD-IS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, isolation, and timing technologies.
The Si828x product line was designed specifically for high-reliability SiC and IGBT gate driving in automotive traction, industrial motor control, and renewable energy systems - emphasizing integrated safety, high CMTI, and simplified system-level certification.
FAQ
What is the isolation voltage rating of the SI8285BD-IS and how is it certified?
The SI8285BD-IS has a 5.0 kVrms isolation rating per UL1577 for 1 minute, verified through factory testing. It also holds CSA approval to IEC 62368-1 (reinforced insulation) and VDE certification to IEC 62368-1. This rating applies specifically to the SI8285BD-IS variant - other Si8285 suffixes (e.g., BC-IS) specify only 3.75 kVrms. The SI8285BD-IS is used in designs where reinforced insulation is mandatory, such as EV traction inverters with >600 VDC bus voltages.
Does the SI8285BD-IS support SiC FETs with 15 V gate drive, and what UVLO threshold does it use?
No - the SI8285BD-IS uses a fixed 9 V UVLO threshold, optimized for SiC FETs requiring lower gate bias (e.g., Wolfspeed C3M0065090D). It is not rated for 15 V gate drive operation; for that, the SI8285ED-IS variant (15 V UVLO) must be selected. The SI8285BD-IS's 9 V UVLO ensures reliable turn-off margin while minimizing gate driver power loss, making it ideal for high-efficiency SiC systems where gate bias is tightly regulated.
How does the Miller clamp (CLMP pin) function in the SI8285BD-IS, and when does it activate?
The CLMP pin in the SI8285BD-IS connects directly to the SiC FET or IGBT gate and sinks Miller current to VSSB. It activates only after the main driver pulls the gate voltage below 2.0 V relative to VSSB - confirmed by an internal comparator - ensuring it never interferes with active switching. This precise timing prevents shoot-through in half-bridge configurations and is a key differentiator from the Si8286 series, which lacks CLMP. The SI8285BD-IS leverages this feature to eliminate external clamp transistors in SiC designs.
Can the SI8285BD-IS be used in automotive applications, and what qualifications does it hold?
Yes - the SI8285BD-IS is available in automotive-grade form (SI8285BD-AS) and is AEC-Q100 qualified. While the SI8285BD-IS itself is the industrial-grade part, its automotive counterpart shares identical electrical parameters, pinout, and packaging. Both variants support PPAP documentation, IMDS/CAMDS listings, and zero-defect manufacturing flows. The SI8285BD-IS is commonly prototyped in automotive systems before transitioning to the -AS version for production.
What is the purpose of the RDY pin on the SI8285BD-IS, and how should it be used in system design?
The RDY pin is a push-pull output indicating that both VDDA (input side) and VDDB (driver side) have exited UVLO and are stable. It goes high only when both rails are fully powered - providing deterministic system startup sequencing. A 10 kΩ pulldown is recommended to prevent false "ready" indications during brown-out conditions. In motor control systems, the MCU waits for RDY high before enabling PWM, ensuring gate drivers are fully operational before switching begins - a critical safeguard in SI8285BD-IS-based SiC inverter designs.
SI8285BD-IS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 125kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 50ns, 50ns
- Pulse Width Distortion (Max):
- 5ns
- Rise / Fall Time (Typ):
- 5.5ns, 8.5ns
- Current - Output High, Low:
- 2A, 4.1A
- Current - Peak Output:
- 4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 10V ~ 30V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UR, VDE
SI8285BD-IS FAQ
1.How can I place an order for SI8285BD-IS through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8285BD-IS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8285BD-IS reliable?
The price and inventory of SI8285BD-IS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8285BD-IS is usually 5 days.
3.What payment methods are accepted for SI8285BD-IS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8285BD-IS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8285BD-IS?
SI8285BD-IS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8285BD-IS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8285BD-IS?
For technical support, including SI8285BD-IS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8285BD-IS requirements.
6.How does Aetrix verify that SI8285BD-IS is sourced from the original manufacturer or authorized distributors?
All SI8285BD-IS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8285BD-IS meets industry standards.
7.What is the process for return or replacement of SI8285BD-IS?
All SI8285BD-IS units undergo pre-shipment inspection (PSI). If there is an issue with SI8285BD-IS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8285BD-IS part is unused and in its original packaging.
Return procedure for SI8285BD-IS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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