Skyworks Solutions Inc. SI8285CD-IS

Overview

SI8285CD-IS from Skyworks is a reinforced-isolation, SiC FET–ready dual-channel gate driver with integrated desaturation detection, soft shutdown, Miller clamp, and power-ready signaling. It delivers 2.7 A peak high-side output current, supports 30 V driver supply (VDDB–VSSB), features 5.0 kVrms isolation per UL1577, and operates across –40 to +125 °C for traction inverter and on-board charger applications.

For engineers reviewing the SI8285CD-IS datasheet, SI8285CD-IS pinout, SI8285CD-IS application, or SI8285CD-IS equivalent, key selection considerations include its 12 V UVLO threshold, separate VH/VL outputs for independent rise/fall control, integrated Miller clamp for half-bridge SiC FETs, DESAT blanking via external CBL, and automotive-grade AEC-Q100 qualification.

Technical Context

The SI8285CD-IS implements RF-based capacitive isolation with 125 kV/µs CMTI, enabling robust noise immunity in high-dV/dt motor drive environments. Its input side accepts complementary CMOS-level IN+/IN− signals and provides active-high RDY and open-drain FLTb feedback to the controller.

On the output side, it drives SiC FETs or IGBTs using discrete VH (pull-up) and VL (pull-down) terminals, each with verified RDS(ON) of 2.48 Ω and 0.86 Ω respectively. Fault response includes sub-1 µs DESAT detection, controlled soft shutdown via internal 60 Ω impedance, and automatic gate clamping through CLMP when VL pulls gate near VSSB.

Key Specifications

Pinout & Package

SI8285CD-IS is housed in a 16-pin wide-body SOIC package (WB SOIC-16) with creepage/clearance ≥8.3 mm and reinforced insulation per IEC 62368-1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated gate driver applications.

Compared with SI8285CC-IS, SI8285CD-IS adds automotive-grade manufacturing, PPAP support, and full AEC-Q100 compliance-making it mandatory for OEM traction systems. Versus UCC5390SCDR, SI8285CD-IS integrates critical safety functions (Miller clamp, RDY, soft shutdown) that reduce design risk and validation effort in high-reliability SiC applications.

Availability

SI8285CD-IS is available at Aetrix Electronics and suitable for traction inverters, on-board chargers, and isolated DC-DC converters requiring stable component supply across automotive production lifecycles.

Supply support for SI8285CD-IS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.

The Si828x product line was designed specifically for high-reliability SiC and IGBT gate driving in electric vehicle powertrains and renewable energy systems, emphasizing system-level safety, thermal robustness, and AEC-Q100 compliance.

FAQ

What is the UVLO threshold for SI8285CD-IS and how does it affect SiC FET operation?

The SI8285CD-IS has a 12 V UVLO threshold on the driver supply (VDDB–VMID). This ensures the gate driver remains disabled until sufficient voltage is present to fully enhance the SiC FET's gate, preventing partial turn-on and associated conduction losses or thermal runaway. The 12 V threshold aligns with recommended gate bias ranges for commercial 1200 V SiC FETs, and its hysteresis prevents chatter during supply ramp-up. SI8285CD-IS maintains this specification across its full –40 to +125 °C operating range.

Does SI8285CD-IS support Miller clamping, and how is it implemented?

Yes, SI8285CD-IS integrates a dedicated Miller clamp function via the CLMP pin. After the VL output pulls the gate toward VSSB, an internal comparator detects when gate voltage falls below 2.0 V relative to VSSB and activates the CLMP NMOS to clamp the gate directly to VSSB. This prevents parasitic turn-on caused by dV/dt coupling through the SiC FET's drain-to-gate capacitance. SI8285CD-IS implements this without external transistors, simplifying layout and improving reliability in half-bridge configurations.

How does the DESAT detection circuit in SI8285CD-IS differ from discrete implementations?

The SI8285CD-IS integrates a complete DESAT sensing path-including a 7 V threshold comparator, 220 mV hysteresis, internal current source for CBL charging, and blanking timer control-eliminating the need for external op-amps, comparators, or timers. Its DSAT pin interfaces directly with the SiC FET drain via RDSAT and DDSAT, and the blanking time is programmable via external CBL (tBlanking = CBL × 7 V / Ichg). SI8285CD-IS achieves <1 µs fault detection latency, significantly faster than typical discrete solutions with propagation delays exceeding 500 ns.

Can SI8285CD-IS be used in systems requiring functional safety certification such as ISO 26262?

Yes, SI8285CD-IS supports ISO 26262 ASIL-B development through its AEC-Q100 Grade 0 qualification, integrated safety features (DESAT, soft shutdown, RDY, FLTb), and PPAP documentation support. Its failure modes-including stuck-at-fault on FLTb, loss of RDY assertion under UVLO, and guaranteed soft shutdown activation on DESAT-are documented in Skyworks' safety manual. SI8285CD-IS enables systematic capability compliance when combined with appropriate MCU-level diagnostics and hardware redundancy, as validated in AN1306 and automotive reference designs.

What is the purpose of the RDY pin on SI8285CD-IS and how should it be used in multi-driver systems?

The RDY pin on SI8285CD-IS is a push-pull output that goes high only when both VDDA and VDDB exceed their respective UVLO thresholds-confirming full power readiness on both sides of the isolation barrier. In multi-driver systems, RDY signals can be logically ANDed to ensure all gate drivers are powered before enabling PWM, preventing partial activation and shoot-through. SI8285CD-IS requires a 10 kΩ pulldown on RDY if unused to avoid false "ready" indications during cold start. Its timing aligns with internal power-on-reset sequencing, making it suitable for synchronized initialization in traction inverter stacks.