Skyworks Solutions Inc. SI82E39AEC-IS1R
- Part No.:
- SI82E39AEC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E39AEC-IS1R.pdf
- Description:
- 3.75 KV 2-CHANNEL ISOLATED VALUE
- Quantity:
- Payment:

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Inventory:4,171
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Product details
Overview
SI82E39AEC-IS1R from Skyworks Solutions is a dual-channel isolated gate driver with 6 A peak output current, universal configuration (independent VIA/VIB inputs), and enable (EN) control. It delivers <5 ns channel-to-channel skew, 200 kV/µs CMTI, and 6 kVRMS reinforced isolation for driving SiC/GaN FETs in half-bridge topologies. Used in onboard chargers and motor drives where precise timing and high noise immunity are critical.
For engineers reviewing the SI82E39AEC-IS1R datasheet, SI82E39AEC-IS1R pinout, SI82E39AEC-IS1R application, or SI82E39AEC-IS1R equivalent, key selection criteria include its universal input architecture, programmable dead time via DT pin, UVLO thresholds (4/8/12/15 V options), voltage-mode drive compatibility with external gate resistors, and AEC-Q100 qualification for automotive power systems.
Technical Context
The SI82E39AEC-IS1R implements capacitive silicon-dioxide isolation with differential RF-modulated OOK signaling, enabling robust noise immunity and tight timing matching across temperature and lifetime. Its dual independent CMOS inputs (VIA/VIB) feed two isolated voltage-source output stages, each with dedicated VDDA/GNDA and VDDB/GNDB supplies.
Dead time is programmable via an external resistor on the DT pin (10–110 kΩ), generating 1.73×RDT + 5.74 ns delay, while overlap protection forces both outputs low during simultaneous high inputs to prevent shoot-through. EN input provides active-high global enable with defined timing (tDID, tEID) and unconditional low-state clamping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 6 kVRMS for 1 minute - meets UL 1577, VDE 60747-17, and CSA 62368-1 reinforced insulation requirements. |
| Channel-to-Channel Skew | <5 ns - ensures precise synchronous switching in high-frequency half-bridge and inverter designs. |
| CMTI | >200 kV/µs - prevents false triggering in noisy high-dv/dt environments like SiC/GaN power stages. |
| Peak Output Current | 6 A sourcing/sinking - supports fast gate charging of high-capacitance wide-bandgap FETs without external buffers. |
| Input Supply Range | 3–20 V - compatible with 3.3 V, 5 V, and 15 V controller logic, including automotive microcontrollers. |
| UVLO Thresholds | 4 V, 8 V, 12 V, or 15 V - configurable per device variant to match gate driver supply rails and prevent partial turn-on. |
| Operating Temperature | –40 to +125 °C - qualified per AEC-Q100 Grade 1 for under-hood automotive applications. |
Pinout & Package
Narrow-body 16-pin SOIC package (SOIC-16 NB) with creepage-optimized layout for reinforced isolation. Pin 1 marked; pins 12 and 13 are NC; pin 11 is EN (active-high enable).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for Channel A | Directly controls VOA output state; CMOS-compatible with Schmitt trigger and deglitch filter. |
| VIB | Non-inverting logic input for Channel B | Directly controls VOB output state; independent of VIA, enabling asymmetric PWM or phase-shifted control. |
| EN | Active-high enable input | When low, forces VOA and VOB low unconditionally; resumes operation within tEID after rising edge. |
| DT | Dead time programming terminal | Resistor-to-GND sets inter-channel delay; connection to VDDI disables dead time and overlap protection. |
| VDDA / GNDA | Channel A gate driver supply and ground | Independent 5–30 V rail powers Channel A output stage; enables bootstrap or isolated supply configurations. |
| VDDB / GNDB | Channel B gate driver supply and ground | Independent 5–30 V rail powers Channel B output stage; allows asymmetrical gate drive voltages per channel. |
| VDDI / GNDI | Logic input supply and ground | 3–20 V domain powers isolation barrier and input logic; galvanically separated from gate driver domains. |
| VOA / VOB | Isolated gate driver outputs | Voltage-mode outputs with internal short-circuit clamp and shutdown clamp for unpowered conditions. |
Key Features
| Feature | Design Value |
|---|---|
| Universal input architecture | Independent VIA/VIB inputs support flexible control schemes (e.g., phase-shifted, complementary, or asynchronous PWM). |
| Voltage-mode drive with external RG | Enables precise tuning of dV/dt, EMI, and overshoot via discrete gate resistors-no current-source limitations. |
| Programmable dead time + overlap protection | Prevents shoot-through in half-bridge topologies without requiring external logic; DT pin resistor sets delay from 1.73×RDT+5.74 ns. |
| AEC-Q100 Grade 1 qualification | Validated for automotive powertrain and charging systems with full temperature, reliability, and defectivity testing. |
| 1500 VRMS working voltage | Supports long-term operation at high bus voltages (e.g., 800 V EV systems) with margin for transients and aging. |
| 4 kV HBM ESD rating | Robust handling of assembly and board-level electrostatic discharge without latch-up or parametric shift. |
Applications
| Onboard Chargers (OBC) | Motor Drives |
|---|---|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV charging systems using SiC half-bridges. IC Role / Device Role / Timing Role: Isolated gate driver for high-side/low-side SiC FETs in interleaved totem-pole PFC and CLLC resonant converters. Use Value: Sub-5 ns skew and 200 kV/µs CMTI maintain timing integrity across 100+ kHz switching, minimizing conduction losses and thermal stress. |
Use Scenario: Field-oriented control (FOC) of 3-phase BLDC or PMSM motors in electric power steering and traction inverters. IC Role / Device Role / Timing Role: Dual-channel isolated driver providing independent gate control for upper/lower leg pairs with programmable dead time. Use Value: EN pin enables immediate fault shutdown across all phases; UVLO thresholds match 12 V/15 V gate supply rails to prevent partial turn-on. |
| Uninterruptible Power Supplies (UPS) | Isolated Switched-Mode Supplies |
Use Scenario: High-efficiency double-conversion UPS with 400 V–800 V DC link and SiC-based inverter stage. IC Role / Device Role / Timing Role: Gate driver for half-bridge legs in three-level NPC or T-type inverter topologies. Use Value: 6 kVRMS isolation and reinforced insulation certifications (UL, VDE, CSA) satisfy safety requirements for medical and datacenter UPS. |
Use Scenario: High-density isolated DC-DC converters (e.g., 48 V–12 V) using active clamp forward or LLC topologies. IC Role / Device Role / Timing Role: Universal-input driver controlling synchronous rectifiers and primary-side switches with independent timing. Use Value: Independent VDDA/VDDB supplies allow optimized gate voltages per switch (e.g., 12 V for MOSFETs, 18 V for GaN), improving efficiency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Silicon Labs SI8239AD-IS1R | Same Si82Ex family, identical pinout and specs, but with disable (DIS) instead of enable (EN) logic polarity. | Requires inverted control signal from MCU; no change to gate drive circuitry or timing behavior. | Select when system control logic uses active-low fault or disable signals. |
| TI UCC5390SCDW | 6 A dual-channel isolator with 3.75 kVRMS isolation, 100 kV/µs CMTI, and integrated Miller clamp; no programmable dead time. | Lacks DT pin and overlap protection; requires external dead time generation or controller-level coordination. | Choose for cost-sensitive industrial supplies where lower isolation/CMTI suffices and dead time is managed externally. |
Compared with SI82E39AEC-IS1R, SI8239AD-IS1R offers identical performance with inverted enable polarity, while UCC5390SCDW trades isolation strength and integrated protection for lower cost and simpler integration in non-automotive applications.
Availability
SI82E39AEC-IS1R is available at Aetrix Electronics and suitable for onboard chargers, motor drives, and uninterruptible power supplies requiring stable component supply, automotive-grade reliability, and reinforced safety certification.
Supply support for SI82E39AEC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si82Ex family was designed specifically for high-reliability isolated gate driving in automotive, industrial, and energy infrastructure applications-emphasizing CMTI, timing precision, and safety certification compliance.
FAQ
What is the isolation rating and safety certification status of the SI82E39AEC-IS1R?
The SI82E39AEC-IS1R provides 6 kVRMS isolation for one minute and is certified to UL 1577, VDE 60747-17 (reinforced insulation), CSA 62368-1, and CSA 60601-1 (2 MOPP). These approvals confirm its suitability for medical, industrial, and automotive applications requiring reinforced insulation barriers between logic and power domains.
Does the SI82E39AEC-IS1R support both high-side/low-side and dual independent configurations?
Yes, the SI82E39AEC-IS1R is a universal-configuration device with independent VIA and VIB inputs, enabling dual independent operation. When the DT pin is connected to VDDI, dead time and overlap protection are disabled, allowing it to function as a true dual driver. For high-side/low-side use, connect DT to GND via a resistor to program inter-channel delay.
What are the UVLO threshold options available for the SI82E39AEC-IS1R?
The SI82E39AEC-IS1R offers factory-configured UVLO thresholds of 4 V, 8 V, 12 V, or 15 V on VDDI, VDDA, and VDDB supplies. These thresholds are fixed per device variant and selected at order time; they prevent erroneous switching during brown-out conditions and ensure gate drivers remain off until supply rails reach safe operating levels.
How does the EN pin behave during power-up and fault conditions in the SI82E39AEC-IS1R?
The EN pin on the SI82E39AEC-IS1R is active-high. When pulled low, it forces both VOA and VOB to logic low within tDID (typ. 25 ns), regardless of input states or supply conditions. After EN rises above VIH, normal operation resumes within tEID (typ. 40 ns). If VDDI is in UVLO, EN has no effect-the outputs remain low until VDDI exits UVLO.
Can the SI82E39AEC-IS1R drive SiC and GaN FETs effectively, and what design considerations apply?
Yes, the SI82E39AEC-IS1R is explicitly validated for SiC and GaN FETs, delivering 6 A peak current and supporting gate drive voltages up to 30 V. Designers must select external gate resistors (RG) to control dV/dt and minimize EMI, leverage the 200 kV/µs CMTI to reject high dv/dt noise, and use the shutdown clamp to prevent parasitic turn-on during unpowered states-critical for wide-bandgap devices with low gate thresholds.
SI82E39AEC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
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- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
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- Approval Agency:
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SI82E39AEC-IS1R FAQ
1.How can I place an order for SI82E39AEC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E39AEC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E39AEC-IS1R reliable?
The price and inventory of SI82E39AEC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E39AEC-IS1R is usually 5 days.
3.What payment methods are accepted for SI82E39AEC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E39AEC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E39AEC-IS1R?
SI82E39AEC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E39AEC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E39AEC-IS1R?
For technical support, including SI82E39AEC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E39AEC-IS1R requirements.
6.How does Aetrix verify that SI82E39AEC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI82E39AEC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E39AEC-IS1R meets industry standards.
7.What is the process for return or replacement of SI82E39AEC-IS1R?
All SI82E39AEC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E39AEC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E39AEC-IS1R part is unused and in its original packaging.
Return procedure for SI82E39AEC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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