My Inquiry
My Account
Skyworks Solutions Inc. SI82E39BCC-IS1R
- Part No.:
- SI82E39BCC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E39BCC-IS1R.pdf
- Description:
- 3.75 KV 2-CHANNEL ISOLATED VALUE
- Quantity:
- Payment:
- Shipping:
Inventory:3,061
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI82E39BCC-IS1R from Skyworks Solutions is a dual-channel isolated gate driver with 6 A peak output current, universal configuration (independent VIA/VIB inputs), and enable (EN) control logic. It delivers <5 ns channel-to-channel skew, 200 kV/µs CMTI, and 6 kVRMS reinforced isolation for driving SiC/GaN FETs in half-bridge topologies. Used in onboard chargers and motor drives requiring precise timing and high noise immunity.
For engineers reviewing the SI82E39BCC-IS1R datasheet, SI82E39BCC-IS1R pinout, SI82E39BCC-IS1R application, or SI82E39BCC-IS1R equivalent, key selection criteria include its universal input architecture, programmable dead time via DT pin, UVLO thresholds (4/8/12/15 V options), voltage-mode drive compatibility with external gate resistors, and AEC-Q100 qualification for automotive power systems.
Technical Context
The SI82E39BCC-IS1R implements capacitive silicon-dioxide (SiO₂) isolation with differential RF-modulated OOK signaling, enabling robust fault tolerance and sub-5 ns skew between channels. Its dual independent CMOS inputs (VIA/VIB) feed two isolated voltage-source output stages, each with dedicated VDDA/GNDA and VDDB/GNDB supplies.
Dead time is programmable via an external resistor on the DT pin (10–110 kΩ), generating 1.73×RDT + 5.74 ns delay; connecting DT to VDDI disables dead time and overlap protection for dual-driver operation. UVLO monitors VDDI, VDDA, and VDDB independently with hysteresis, and thermal shutdown triggers at TSD+ with weak-pull-down recovery below TSD−.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 6 kVRMS for 1 minute - meets UL 1577, VDE 60747-17, and CSA 62368-1 reinforced insulation requirements. |
| Channel Skew | <5 ns - enables precise synchronous switching in high-frequency half-bridge inverters without shoot-through risk. |
| CMTI | >200 kV/µs - ensures reliable operation in noisy high-dv/dt environments like SiC/GaN-based motor drives. |
| Peak Output Current | 6 A sourcing/sinking - supports fast gate charging of high-capacitance wide-bandgap FETs with external RG tuning. |
| Input Supply Range | 3–20 V - compatible with standard MCU I/O levels and industrial logic interfaces without level-shifting. |
| Operating Temp | –40 to +125 °C - qualified per AEC-Q100 Grade 1 for under-hood automotive applications including OBCs. |
| UVLO Thresholds | 4 V / 8 V / 12 V / 15 V options - prevents erratic switching during brown-out conditions in DC-DC and inverter control loops. |
| Package | Narrow-body SOIC-16 - provides 8 mm creepage/clearance and fits space-constrained PCB layouts in power modules. |
Pinout & Package
Narrow-body 16-pin SOIC (NB SOIC-16) package with 8.0 mm creepage and clearance, RoHS-compliant, and rated for 1500 VRMS working voltage.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for Channel A | Accepts CMOS-level signals; controls VOA directly in universal mode; unaffected by DT pin when DT = VDDI. |
| VIB | Non-inverting logic input for Channel B | Independent control of VOB; enables true dual-driver operation without cross-talk or forced dead time. |
| EN | Active-high enable input | Drives both VOA and VOB low when deasserted; resumes normal operation within tEID after assertion. |
| DT | Dead time programming terminal | Resistor-to-GND sets dead time (1.73×RDT + 5.74 ns); connection to VDDI disables dead time and overlap protection. |
| VDDA / GNDA | Channel A gate driver supply and ground | 5–30 V isolated supply; powers output stage A; independent UVLO monitoring prevents false turn-on during undervoltage. |
| VDDB / GNDB | Channel B gate driver supply and ground | 5–30 V isolated supply; fully independent from VDDA/GNDA; allows asymmetric rail configurations in half-bridge designs. |
| VOA / VOB | High-current gate driver outputs | Voltage-mode outputs with 6 A peak capability; short-circuit clamped to VDDA/B; shutdown clamp pulls low when unpowered. |
| VDDI / GNDI | Logic input supply and ground | 3–20 V digital supply; powers isolation barrier and input logic; UVLO threshold configurable per ordering option. |
Key Features
| Feature | Design Value |
|---|---|
| Universal input architecture | Independent VIA/VIB control enables flexible half-bridge, dual-switch, or phase-shifted topologies without re-layout. |
| Voltage-mode drive with external RG | Allows precise tuning of dV/dt, EMI, and overshoot via discrete gate resistors-no internal current limiting compromises. |
| Programmable dead time & overlap protection | Hardware-enforced shoot-through prevention using DT resistor; overlap logic forces both outputs low on simultaneous high inputs. |
| AEC-Q100 Grade 1 qualification | Validated for automotive powertrain and charging systems operating up to +125 °C ambient with zero latent defects. |
| Robust isolation barrier | Silicon-dioxide capacitive isolation delivers stable timing performance over temperature, life, and voltage stress vs. optocouplers. |
| Integrated shutdown clamp | Active pull-down to GNDA/GNDB prevents parasitic FET turn-on during gate driver power loss or startup sequencing. |
Applications
| Onboard Charger (OBC) | Industrial Motor Drive |
|---|---|
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV charging systems with SiC MOSFETs operating at >100 kHz. IC Role / Device Role / Timing Role: Isolated gate driver for high-side/low-side half-bridge switches; enforces dead time to prevent shoot-through during ZVS transitions. Use Value: Sub-5 ns skew and 200 kV/µs CMTI maintain timing integrity across high dv/dt transients in compact, high-power-density OBC modules. |
Use Scenario: Field-oriented control (FOC) of 3-phase PMSM motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Dual-channel driver for inverter leg pairs; independent VIA/VIB inputs synchronize with PWM timers for precise vector modulation. Use Value: 6 A peak current and voltage-mode drive enable fast SiC gate charging while minimizing switching losses and EMI in 48–400 V systems. |
| Uninterruptible Power Supply (UPS) | Renewable Energy Inverter |
|
Use Scenario: High-efficiency double-conversion UPS with active PFC and battery-backed DC-AC inversion using GaN HEMTs. IC Role / Device Role / Timing Role: Isolated driver for boost PFC stage and inverter stage; EN pin enables system-level fault shutdown across both domains. Use Value: AEC-Q100 qualification and 1500 VRMS working voltage ensure long-term reliability in 24/7 mission-critical backup power infrastructure. |
Use Scenario: String-level solar inverters converting 600–1500 V DC to grid-synchronized AC using SiC MOSFETs in three-level NPC topologies. IC Role / Device Role / Timing Role: Gate driver for high-side and low-side switches in each inverter leg; DT pin configures dead time per leg for optimal efficiency. Use Value: 6 kVRMS isolation and reinforced insulation certifications (UL, VDE, CSA) meet stringent safety standards for rooftop and utility-scale PV installations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8239BD-IS1R | Same NB SOIC-16 package and universal VIA/VIB inputs, but uses DISABLE (DIS) instead of ENABLE (EN) logic. | Requires inverted control signal polarity; not drop-in replaceable due to opposite active-state behavior on control pin. | Select SI8239BD-IS1R only when system controller natively sources active-low disable signals and layout cannot accommodate logic inversion. |
| UCC5390SCD | TI device with 10 A peak output, single PWM input, and fixed 100 ns dead time; no independent VIA/VIB or DT programming. | Limited to high-side/low-side half-bridge use; lacks universal dual-input flexibility and adjustable dead time. | Choose UCC5390SCD only when design mandates higher peak current and accepts fixed dead time, sacrificing configurability for raw drive strength. |
Compared with SI82E39BCC-IS1R, SI8239BD-IS1R offers identical isolation and timing specs but requires control signal inversion, while UCC5390SCD trades programmability and dual-input flexibility for higher peak current and integrated dead time-making SI82E39BCC-IS1R optimal for designs needing precision timing control and topology adaptability.
Availability
SI82E39BCC-IS1R is available at Aetrix Electronics and suitable for onboard chargers, industrial motor drives, and uninterruptible power supplies requiring stable component supply, automotive-grade reliability, and certified reinforced isolation.
Supply support for SI82E39BCC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-performance power and communication systems.
The Si82Ex family was designed specifically for high-reliability isolated gate driving in automotive, industrial, and renewable energy applications-emphasizing low skew, high CMTI, and AEC-Q100 compliance over cost-optimized optocoupler alternatives.
FAQ
What is the maximum gate driver supply voltage supported by the SI82E39BCC-IS1R?
The SI82E39BCC-IS1R supports a maximum gate driver supply voltage of 30 V on both VDDA and VDDB pins. This rating applies across the full operating temperature range (–40 to +125 °C) and enables direct interfacing with common 12 V, 15 V, and 20 V gate drive rails used for SiC and GaN FETs. Operation above 30 V risks permanent damage to the output stage.
Does the SI82E39BCC-IS1R support both high-side/low-side and dual independent switch configurations?
Yes, the SI82E39BCC-IS1R supports both configurations. In universal mode (VIA/VIB inputs), it operates as a dual independent driver. When the DT pin is configured with a resistor to GNDI, it functions as a high-side/low-side driver with programmable dead time and hardware-enforced overlap protection to prevent shoot-through.
How does the EN pin behave during VDDI undervoltage lockout (UVLO)?
When VDDI falls below its UVLO threshold (e.g., 4 V or 8 V depending on variant), the SI82E39BCC-IS1R ignores the EN pin state and forces both VOA and VOB low. The EN pin only becomes functional once VDDI rises above the UVLO hysteresis threshold, ensuring deterministic behavior during power-up and brown-out events.
What is the purpose of the shutdown clamp feature in the SI82E39BCC-IS1R?
The shutdown clamp in the SI82E39BCC-IS1R provides an active pull-down path from VOA/VOB to GNDA/GNDB when VDDA or VDDB is unpowered. This prevents parasitic turn-on of external FETs caused by transient coupling or floating gate voltages during power sequencing or fault conditions-critical for system safety in automotive and industrial inverters.
Can the SI82E39BCC-IS1R drive both SiC and GaN FETs effectively?
Yes, the SI82E39BCC-IS1R is explicitly validated for driving SiC MOSFETs and GaN HEMTs. Its 6 A peak sourcing/sinking current, voltage-mode architecture (compatible with discrete gate resistors), <5 ns skew, and >200 kV/µs CMTI address the fast switching, high dv/dt, and precise timing demands of wide-bandgap power devices in high-frequency converters.
SI82E39BCC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82E39BCC-IS1R FAQ
1.How can I place an order for SI82E39BCC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E39BCC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E39BCC-IS1R reliable?
The price and inventory of SI82E39BCC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E39BCC-IS1R is usually 5 days.
3.What payment methods are accepted for SI82E39BCC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E39BCC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E39BCC-IS1R?
SI82E39BCC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E39BCC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E39BCC-IS1R?
For technical support, including SI82E39BCC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E39BCC-IS1R requirements.
6.How does Aetrix verify that SI82E39BCC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI82E39BCC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E39BCC-IS1R meets industry standards.
7.What is the process for return or replacement of SI82E39BCC-IS1R?
All SI82E39BCC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E39BCC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E39BCC-IS1R part is unused and in its original packaging.
Return procedure for SI82E39BCC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI82E39BCC-IS1R Tags
.JPG)
-
TLP152(TPL,E
Toshiba Semiconductor and Storage
-
HT0740LG-G
Microchip Technology
-
FOD8314TR2
onsemi
-
1EDI60N12AFXUMA1
Infineon Technologies
-
1EDB7275FXUMA1
Infineon Technologies
-
UCC5350MCDR
Texas Instruments
-
2EDB7259KXUMA1
Infineon Technologies
-
UCC5304DWVR
Texas Instruments
-
SI8261BBC-C-ISR
Skyworks Solutions Inc.
-
HT0440LG-G
Microchip Technology
-
HCPL-0302-500E
Broadcom Limited
-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
