Skyworks Solutions Inc. SI82E89AEE-IS3R
- Part No.:
- SI82E89AEE-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E89AEE-IS3R.pdf
- Description:
- 6 KV 2-CHANNEL ISOLATED VALUE GA
- Quantity:
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Product details
Overview
SI82E89AEE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver with high-side/low-side configuration, 6 A peak output drive strength, <5 ns channel-to-channel skew, and 6 kVRMS reinforced isolation. It drives SiC/GaN MOSFETs and IGBTs in half-bridge topologies for onboard chargers and motor inverters.
For engineers reviewing the SI82E89AEE-IS3R datasheet, SI82E89AEE-IS3R pinout, SI82E89AEE-IS3R application, or SI82E89AEE-IS3R equivalent, this page delivers verified functional identity, validated SOIC-16 pin mapping, confirmed UVLO thresholds (4 V/8 V), CMTI > 200 kV/µs, and two rigorously cross-checked alternative parts for half-bridge gate drive replacement.
Technical Context
The SI82E89AEE-IS3R implements capacitive silicon-dioxide isolation with differential RF-modulated OOK signaling, enabling robust noise immunity and precise timing control. Its architecture supports independent PWM input with active-high disable (DIS) and programmable dead time via external resistor on DT pin.
This variant uses High-Side/Low-Side pinout with dedicated PWM input (not VIA/VIB), DIS control, and fixed UVLO thresholds of 4 V (VDDI) and 8 V (VDDA/VDDB). It operates across –40 to +125 °C and integrates shutdown clamp, short-circuit clamp, and thermal shutdown at 150 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6 kVRMS for 1 minute (UL 1577, VDE 60747-17 reinforced) |
| Channel-to-Channel Skew | <5 ns - ensures synchronized switching in half-bridge to prevent shoot-through |
| CMTI | >200 kV/µs - maintains signal integrity in high-dV/dt power converter environments |
| Output Drive Strength | 6 A peak sourcing/sinking - directly drives high-Qg SiC FETs without external buffers |
| UVLO Thresholds | VDDI: 4 V (on), 3.5 V (off); VDDA/VDDB: 8 V (on), 7.5 V (off) - prevents erratic switching during brownout |
| Operating Temperature | –40 to +125 °C - qualified per AEC-Q100 Grade 1 for automotive powertrain use |
| Dead Time Range | Programmable 0–500 ns via 10–110 kΩ RDT - enables fine-tuned overlap protection |
Pinout & Package
Narrow-body 16-pin SOIC (SOIC-16 NB) package with creepage ≥8.3 mm and clearance ≥8.0 mm; RoHS-compliant, halogen-free, and qualified to AEC-Q100.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, VIA | Non-inverting logic input A | Not connected - SI82E89x uses PWM input only; this pin is NC per datasheet Figure 3 |
| 2, VDDA | High-side gate driver supply | Provides 5–30 V power to output stage A; UVLO triggers at 8 V |
| 3, VOA | High-side gate driver output | Sources/sinks up to 6 A; includes short-circuit clamp to VDDA and shutdown clamp to GNDA |
| 4, GNDA | High-side ground reference | Isolated return path for VDDA/VOA; must be separated from low-side ground |
| 5, VDDB | Low-side gate driver supply | Provides 5–30 V power to output stage B; UVLO triggers at 8 V |
| 6, VOB | Low-side gate driver output | Sources/sinks up to 6 A; includes same clamping features as VOA |
| 7, GNDB | Low-side ground reference | Isolated return path for VDDB/VOB; galvanically separated from GNDA |
| 8, VDDI | Logic input supply | 3–20 V CMOS-compatible supply; UVLO triggers at 4 V to block inputs during undervoltage |
| 9, VIB | Non-inverting logic input B | Not connected - SI82E89x uses PWM input only; this pin is NC per datasheet Figure 3 |
| 10, GNDI | Logic input ground | Reference for all digital inputs (PWM, DIS, DT); must be tied to controller ground |
| 11, DT | Dead time programming input | Accepts resistor to GNDI to set dead time; connecting to VDDI disables dead time and overlap protection |
| 12, DIS | Active-high disable input | Drives both VOA and VOB low when high; overrides all logic states for fault-safe shutdown |
| 13, NC | No connection | Internally unconnected; must remain floating or grounded per layout guidelines |
| 14, NC | No connection | Internally unconnected; must remain floating or grounded per layout guidelines |
| 15, NC | No connection | Internally unconnected; must remain floating or grounded per layout guidelines |
| 16, PWM | Single PWM logic input | Drives VOA high / VOB low when high; VOA low / VOB high when low - native half-bridge control |
Key Features
| Feature | Design Value |
|---|---|
| Voltage Mode Drive | Enables precise gate resistor tuning for optimized switching speed, EMI, and voltage overshoot - no current-mode complexity |
| Programmable Dead Time | 0–500 ns via single external resistor (RDT) - eliminates need for external logic or delay networks |
| Integrated Shutdown Clamp | Active pull-down to GNDA/GNDB when VDDA/VDDB is unpowered - prevents parasitic turn-on of FETs |
| Reinforced Isolation | 6 kVRMS rating with 1500 VRMS working voltage and 10 kV bipolar surge - meets UL, VDE, CSA, CQC safety standards |
| AEC-Q100 Qualified | Grade 1 (–40 to +125 °C) qualification across full temperature range - validated for automotive traction inverters and OBCs |
Applications
| Onboard Charger (OBC) | Motor Inverter |
|---|---|
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV charging systems with SiC-based totem-pole PFC and LLC resonant stages. IC Role / Device Role / Timing Role: High-side/low-side gate driver controlling complementary SiC MOSFET pairs in half-bridge configurations with precise dead-time control. Use Value: <5 ns skew and >200 kV/µs CMTI ensure clean switching under high-frequency, high-dV/dt conditions typical of 100+ kHz SiC operation. |
Use Scenario: Traction inverter driving permanent magnet synchronous motors (PMSM) in hybrid/electric vehicles. IC Role / Device Role / Timing Role: Isolated gate driver delivering 6 A peak current to high-Qg IGBTs/SiC FETs with fault-responsive DIS shutdown. Use Value: AEC-Q100 Grade 1 qualification and integrated thermal shutdown enable reliable operation in under-hood environments up to 125 °C ambient. |
| Industrial UPS | Grid-Tied Solar Inverter |
|
Use Scenario: Double-conversion online UPS with IGBT-based inverter stage requiring high reliability and galvanic isolation. IC Role / Device Role / Timing Role: Reinforced-isolation gate driver providing 6 kVRMS barrier between control MCU and 600 V DC bus. Use Value: UL/VDE-certified reinforced insulation eliminates need for external isolation components, reducing BOM count and layout area. |
Use Scenario: String-level solar inverters using SiC MOSFETs in three-phase NPC or T-type topologies. IC Role / Device Role / Timing Role: Dual-channel driver with independent UVLO monitoring per channel for fault-resilient operation across varying PV string voltages. Use Value: Independent VDDA/VDDB UVLO (8 V) prevents partial drive failure during bus voltage sag, improving system fault tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side/low-side isolated gate drive applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Silicon Labs SI8220BD-D-IS | Single-input, 4 A peak drive, SOIC-16, 5 kVRMS isolation, no programmable dead time | Lacks DT pin and overlap protection - requires external dead-time generation logic | Choose for cost-sensitive, lower-power (<3 kW) inverters where dead time is managed by MCU |
| TI UCC5350MCQDWVRQ1 | Single-input, 5 A peak drive, SOIC-16, 5.7 kVRMS, integrated Miller clamp, no deglitch filter | Includes Miller clamp but lacks CMTI > 200 kV/µs and AEC-Q100 Grade 1 temp range | Prefer for automotive applications needing Miller clamping but accepting reduced noise immunity and narrower temp range |
Compared with SI82E89AEE-IS3R, SI8220BD-D-IS offers lower drive strength and no dead-time programmability, while UCC5350MCQDWVRQ1 provides Miller clamping but falls short on CMTI and high-temp reliability - SI82E89AEE-IS3R uniquely balances 6 A drive, <5 ns skew, AEC-Q100 Grade 1, and field-programmable dead time in one SOIC-16 package.
Availability
SI82E89AEE-IS3R is available at Aetrix Electronics and suitable for onboard chargers, motor inverters, and industrial UPS systems requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for SI82E89AEE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si82Ex family was designed specifically for high-reliability, high-efficiency power conversion systems - targeting EV traction inverters, OBCs, and industrial motor drives requiring reinforced isolation, low skew, and AEC-Q100 compliance.
FAQ
What is the function of the DT pin on the SI82E89AEE-IS3R?
The DT pin on the SI82E89AEE-IS3R programs dead time between VOA and VOB transitions using an external resistor to GNDI. Values from 10 kΩ to 110 kΩ yield 0–500 ns dead time. Connecting DT to VDDI disables dead time and overlap protection, allowing pure dual-driver operation. This behavior is confirmed in datasheet Section 4.5 and Figure 18.
Does the SI82E89AEE-IS3R support both high-side and low-side gate driving in a single package?
Yes, the SI82E89AEE-IS3R integrates two fully isolated gate drivers - VOA drives the high-side switch (e.g., upper MOSFET in a half-bridge), and VOB drives the low-side switch (e.g., lower MOSFET), each with independent supplies (VDDA/GNDA and VDDB/GNDB) and reinforced 6 kVRMS isolation between input and outputs.
What UVLO thresholds does the SI82E89AEE-IS3R implement?
The SI82E89AEE-IS3R implements three independent UVLO monitors: VDDI enters UVLO at ≤3.5 V and exits at >4.0 V; VDDA and VDDB each enter UVLO at ≤7.5 V and exit at >8.0 V. These values are fixed for the SI82E89x variant and prevent erroneous switching during supply brownouts.
Is the SI82E89AEE-IS3R qualified for automotive applications?
Yes, the SI82E89AEE-IS3R is AEC-Q100 Grade 1 qualified (–40 to +125 °C) and manufactured using automotive-specific process flows. It meets reinforced insulation requirements per UL 1577, VDE 60747-17, and CSA 62368-1 - making it suitable for EV onboard chargers and traction inverters.
How does the DIS pin behave when asserted on the SI82E89AEE-IS3R?
When the DIS pin is driven high, the SI82E89AEE-IS3R unconditionally forces both VOA and VOB low within tDID (max 35 ns), overriding all input states including PWM. Operation resumes within tEID (max 45 ns) after DIS returns low. This behavior is defined in datasheet Table 3 and Section 4.4.2.
SI82E89AEE-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82E89AEE-IS3R FAQ
1.How can I place an order for SI82E89AEE-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E89AEE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E89AEE-IS3R reliable?
The price and inventory of SI82E89AEE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E89AEE-IS3R is usually 5 days.
3.What payment methods are accepted for SI82E89AEE-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E89AEE-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E89AEE-IS3R?
SI82E89AEE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E89AEE-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E89AEE-IS3R?
For technical support, including SI82E89AEE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E89AEE-IS3R requirements.
6.How does Aetrix verify that SI82E89AEE-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82E89AEE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E89AEE-IS3R meets industry standards.
7.What is the process for return or replacement of SI82E89AEE-IS3R?
All SI82E89AEE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E89AEE-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E89AEE-IS3R part is unused and in its original packaging.
Return procedure for SI82E89AEE-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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