Skyworks Solutions Inc. SI82E99AEC-IS1R
- Part No.:
- SI82E99AEC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E99AEC-IS1R.pdf
- Description:
- 3.75 KV 2-CHANNEL ISOLATED VALUE
- Quantity:
- Payment:

- Shipping:

Inventory:4,909
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Product details
Overview
SI82E99AEC-IS1R from Skyworks Solutions is a dual-channel isolated gate driver with high-side/low-side configuration, 6 A peak output drive, <5 ns channel-to-channel skew, and 6 kVRMS reinforced isolation. It operates with 3–20 V logic supply and 5–30 V gate supply, and is designed for half-bridge SiC/GaN FET control in automotive-grade power inverters.
For engineers reviewing the SI82E99AEC-IS1R datasheet, SI82E99AEC-IS1R pinout, SI82E99AEC-IS1R application, or SI82E99AEC-IS1R equivalent, key selection considerations include its AEC-Q100 qualification, programmable dead time via DT pin, UVLO thresholds (4/8/12/15 V), CMTI > 200 kV/μs, and compatibility with universal or high-side/low-side topologies.
Technical Context
The SI82E99AEC-IS1R implements RF-modulated capacitive isolation using dual silicon dioxide (SiO₂) capacitors per channel, enabling differential signal transmission with OOK modulation. Its architecture delivers deterministic timing, minimal temperature drift, and tight part-to-part matching.
This variant uses a PWM input architecture with dedicated EN enable control, supports dead time insertion between VOA and VOB outputs, and integrates independent UVLO monitoring on VDDI, VDDA, and VDDB rails. Output stage operates in voltage-mode drive with external gate resistor tuning for switching speed and overshoot control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 6 kVRMS for 1 minute - certified reinforced insulation per UL 1577, VDE 60747-17, CSA 62368-1 |
| Channel-to-Channel Skew | <5 ns - ensures precise timing alignment between high-side and low-side gate drive edges |
| CMTI | >200 kV/μs - prevents false triggering in noisy high-dV/dt environments like motor drives |
| Peak Output Current | 6 A sourcing/sinking - sufficient to drive high-gate-charge SiC and GaN FETs at fast slew rates |
| Logic Input Supply Range | 3–20 V - compatible with 3.3 V, 5 V, and 15 V controller interfaces without level shifting |
| Gate Supply Range | 5–30 V - supports bipolar gate biasing and wide-range bootstrap operation |
| Operating Temperature | –40 to +125 °C - meets automotive under-hood thermal requirements |
| UVLO Thresholds | 4 V, 8 V, 12 V, 15 V - configurable per device option to match system rail sequencing |
Pinout & Package
Narrow-body 16-pin SOIC package (7.5 mm × 10.3 mm, 1.27 mm pitch) with creepage ≥8.3 mm and clearance ≥8.0 mm per IEC 60664-1.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 VIA | PWM logic input | Single-input control for both channels; synchronizes VOA/VOB complementary transitions |
| 2 VDDA | High-side gate driver supply | Provides power to output stage A; supports bootstrap or isolated supply configurations |
| 3 VOA | High-side gate driver output | Voltage-mode output driving high-side FET gate; clamped to VDDA during short-circuit |
| 4 GNDA | High-side ground reference | Return path for high-side driver; galvanically isolated from logic side |
| 5 VDDB | Low-side gate driver supply | Power for output stage B; typically tied to main system rail |
| 6 VOB | Low-side gate driver output | Voltage-mode output driving low-side FET gate; includes active pull-down clamp when unpowered |
| 7 GNDB | Low-side ground reference | Return path for low-side driver; referenced to system ground |
| 8 VDDI | Logic input supply | 3–20 V CMOS-compatible supply for input circuitry and isolation barrier |
| 9 VIB | Not connected | No internal bond; must remain floating or grounded per layout guidelines |
| 10 GNDI | Logic input ground | Reference for all digital inputs; isolated from GNDA/GNDB by reinforced barrier |
| 11 DT | Dead time programming | Resistor-to-ground sets dead time (10–110 kΩ → ~18–200 ns); tie to VDDI to disable |
| 12 EN | Active-high enable | Asserted high enables normal operation; deasserted low forces VOA/VOB low unconditionally |
| 13 NC | No connection | Internal die pad not bonded; leave unconnected |
| 14 NC | No connection | Internal die pad not bonded; leave unconnected |
| 15 NC | No connection | Internal die pad not bonded; leave unconnected |
| 16 VDDI | Logic input supply (duplicate) | Second VDDI pin for improved decoupling and current distribution |
Key Features
| Feature | Design Value |
|---|---|
| Voltage Mode Drive | Enables predictable gate current control via external resistors-no need for complex current-source design |
| Programmable Dead Time | Adjustable 18–200 ns via single external resistor on DT pin-prevents shoot-through in half-bridge topologies |
| AEC-Q100 Qualified | Grade 1 (–40 to +125 °C) qualification with automotive-specific manufacturing flow and defectivity controls |
| Shutdown Clamp | Active pull-down on VOA/VOB when VDDA/B is unpowered-eliminates parasitic turn-on of driven FETs |
| Short-Circuit Clamp | Internal diode clamps VOA/VOB to VDDA/B during overvoltage events-protects gate oxide of SiC/GaN devices |
| CMOS Inputs with Deglitch Filter | Configurable noise rejection on PWM/EN pins-suppresses sub-100 ns transients without compromising propagation delay |
Applications
| Motor Drives | Onboard Chargers |
|---|---|
Use Scenario: Three-phase inverter controlling PMSM or induction motors in EV traction and industrial servo systems. IC Role / Device Role / Timing Role: High-side/low-side gate driver delivering synchronized, shoot-through–free gate signals to SiC MOSFET half-bridges. Use Value: <5 ns skew and >200 kV/μs CMTI ensure clean commutation under high dV/dt bus transients and EMI-rich motor environments. |
Use Scenario: Bidirectional AC/DC and DC/DC conversion in electric vehicle onboard chargers (OBC). IC Role / Device Role / Timing Role: Isolated gate driver for interleaved LLC or phase-shifted full-bridge topologies with synchronous rectification. Use Value: 6 kVRMS reinforced isolation and AEC-Q100 qualification meet automotive safety and reliability requirements for 11 kW+ OBC designs. |
| Power Inverters | Uninterruptible Power Supplies |
Use Scenario: Solar string inverters and energy storage system (ESS) inverters operating at 1000 V DC bus. IC Role / Device Role / Timing Role: Dual-channel isolated driver controlling high-voltage SiC half-bridges with programmable dead time and UVLO staging. Use Value: 30 V max gate supply and 6 A drive support fast switching of high-Qg SiC FETs while maintaining safe SOA margins. |
Use Scenario: Online double-conversion UPS systems requiring high-efficiency, high-reliability DC/AC inversion. IC Role / Device Role / Timing Role: Gate driver for IGBT or SiC-based three-level NPC or T-type inverter stages. Use Value: Reinforced insulation certifications (UL, VDE, CSA) and 1500 VRMS working voltage satisfy UL 1778 and IEC 62040-1 safety mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si82E99AD-IS1R | Same pinout and isolation specs, but features DIS (disable) instead of EN (enable) control logic | Preferred in systems where fault response requires active-high disable assertion rather than active-high enable | Select based on controller interface polarity: SI82E99AEC-IS1R requires EN = high for operation; SI82E99AD-IS1R requires DIS = low |
| UCC5390SCD | TI device with 10 A peak drive, integrated Miller clamp, and 5.7 kVRMS isolation; different pinout and no DT pin | Better suited for ultra-fast SiC switching with critical Miller immunity; lacks programmable dead time | Choose SI82E99AEC-IS1R when dead time tuning and AEC-Q100 compliance are mandatory; UCC5390SCD when higher drive strength and Miller clamping are prioritized |
Compared with SI82E99AD-IS1R, SI82E99AEC-IS1R offers identical isolation and timing performance but differs in control logic polarity; versus UCC5390SCD, it trades peak current and Miller protection for programmable dead time, automotive qualification, and direct replacement in existing Si82Ex layouts.
Availability
SI82E99AEC-IS1R is available at Aetrix Electronics and suitable for automotive onboard chargers, industrial motor drives, solar inverters, and uninterruptible power supplies requiring stable component supply across extended product lifecycles.
Supply support for SI82E99AEC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si82Ex family was developed to replace optocoupled gate drivers in high-reliability power systems, delivering superior CMTI, lifetime stability, and AEC-Q100-compliant performance for EV, industrial, and renewable energy applications.
FAQ
What is the isolation rating and safety certification status of the SI82E99AEC-IS1R?
The SI82E99AEC-IS1R provides 6 kVRMS reinforced isolation rated for one minute and is certified to UL 1577, VDE 60747-17, CSA 62368-1, and CQC GB4943.1. It supports 1500 VRMS working voltage and meets 2 MOPP requirements per IEC 60601-1, making it suitable for medical and automotive high-voltage isolation barriers.
Does the SI82E99AEC-IS1R support both high-side/low-side and dual independent configurations?
The SI82E99AEC-IS1R is configured specifically for high-side/low-side operation using a single PWM input. It does not support universal (dual independent) mode. For dual independent control, SI82E29x or SI82E39x variants with VIA/VIB inputs must be selected instead of SI82E99AEC-IS1R.
How is dead time programmed on the SI82E99AEC-IS1R, and what is the range?
Dead time on the SI82E99AEC-IS1R is set by connecting an external resistor (RDT) from the DT pin to GNDI. With RDT = 10–110 kΩ, dead time ranges from ~18 ns to ~200 ns. Connecting DT to VDDI disables dead time insertion and overlap protection, forcing complementary PWM behavior without delay.
What UVLO thresholds are implemented in the SI82E99AEC-IS1R, and how are they selected?
The SI82E99AEC-IS1R includes factory-configured UVLO thresholds of 4 V, 8 V, 12 V, and 15 V on VDDI, VDDA, and VDDB rails. Threshold selection is fixed per orderable part number and cannot be adjusted externally; the specific UVLO levels for SI82E99AEC-IS1R are documented in Skyworks' ordering guide as 12 V on VDDI and 8 V on VDDA/VDDB.
Is the SI82E99AEC-IS1R pin-compatible with other Si82Ex family members?
The SI82E99AEC-IS1R shares the same narrow-body SOIC-16 footprint and pinout as SI82E89x and SI82E99x variants, including identical placement of PWM, EN, DT, VDDI, VDDA, VDDB, VOA, VOB, GNDA, GNDB, GNDI, and NC pins. It is not pin-compatible with SI82E29x/SI82E39x (VIA/VIB input) or wide-body SOIC-14/LGA-13 variants.
SI82E99AEC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82E99AEC-IS1R FAQ
1.How can I place an order for SI82E99AEC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E99AEC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E99AEC-IS1R reliable?
The price and inventory of SI82E99AEC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E99AEC-IS1R is usually 5 days.
3.What payment methods are accepted for SI82E99AEC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E99AEC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E99AEC-IS1R?
SI82E99AEC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E99AEC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E99AEC-IS1R?
For technical support, including SI82E99AEC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E99AEC-IS1R requirements.
6.How does Aetrix verify that SI82E99AEC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI82E99AEC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E99AEC-IS1R meets industry standards.
7.What is the process for return or replacement of SI82E99AEC-IS1R?
All SI82E99AEC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E99AEC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E99AEC-IS1R part is unused and in its original packaging.
Return procedure for SI82E99AEC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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