Skyworks Solutions Inc. SI82E99AEE-IS3R
- Part No.:
- SI82E99AEE-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E99AEE-IS3R.pdf
- Description:
- 6 KV 2-CHANNEL ISOLATED VALUE GA
- Quantity:
- Payment:

- Shipping:

Inventory:4,722
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI82E99AEE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver with high-side/low-side configuration, 6 A peak output drive strength, <5 ns channel-to-channel skew, and 6 kVRMS reinforced isolation. It operates with 3–20 V logic supply and 5–30 V gate supply, and is designed for half-bridge SiC/GaN/MOSFET/IGBT control in onboard chargers and motor drives.
For engineers reviewing the SI82E99AEE-IS3R datasheet, SI82E99AEE-IS3R pinout, SI82E99AEE-IS3R application, or SI82E99AEE-IS3R equivalent, this page delivers verified functional identity, validated SOIC-16 narrow-body package mapping, confirmed PWM-input + EN-control architecture, safety-certified isolation specs, and two rigorously cross-checked alternative parts for half-bridge gate driving.
Technical Context
The SI82E99AEE-IS3R implements a high-side/low-side dual-output topology using capacitive silicon-dioxide (SiO₂) isolation with RF OOK modulation, delivering 200 kV/µs CMTI and deterministic timing behavior across –40 to 125 °C. Its PWM input accepts standard logic-level signals while EN enables synchronous shutdown of both outputs.
Dead time is programmable via external resistor on DT pin (10–110 kΩ), enabling precise shoot-through prevention in half-bridge configurations. UVLO thresholds are fixed at 4 V (VDDI), 8 V (VDDA), and 8 V (VDDB), with independent monitoring per power domain and active pull-down clamps during unpowered states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6 kVRMS for 1 minute (UL 1577), reinforced insulation per IEC 62368-1 & IEC 60747-17 |
| Output Drive Strength | ±6 A peak sourcing/sinking - supports fast switching of high-Qg SiC/GaN FETs without external buffers |
| Channel Skew | <5 ns - ensures tight timing alignment between high-side and low-side gate signals |
| CMTI | >200 kV/µs - maintains signal integrity in noisy high-dV/dt power converter environments |
| Logic Input Type | CMOS-compatible, Schmitt-triggered, deglitched - rejects noise spikes & ensures clean edge detection |
| UVLO Thresholds | VDDI: 4 V (on), 3.5 V (off); VDDA/VDDB: 8 V (on), 7.5 V (off) - prevents erratic switching during brownout |
| Operating Temp | –40 to +125 °C - qualified per AEC-Q100 Grade 1 for automotive powertrain and charging systems |
Pinout & Package
Narrow-body 16-pin SOIC (SOIC-16 NB) package with creepage ≥8.3 mm and clearance ≥8.0 mm; RoHS-compliant, halogen-free, Pb-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDI | Logic input power supply | 3–20 V supply for internal digital logic and isolator modulator; powers CMOS inputs and EN/DIS circuitry |
| GNDI | Logic input ground | Reference for all digital inputs (PWM, EN); galvanically isolated from GNDA/GNDB |
| PWM | Single logic input for both channels | Drives VOA high / VOB low when high; VOA low / VOB high when low - enables complementary half-bridge operation |
| EN | Active-high enable control | When low, forces VOA and VOB low unconditionally; resumes normal PWM operation within tEID (~50 ns) after rising edge |
| DT | Dead time programming terminal | Resistor-to-GND sets dead time (10–110 kΩ → ~17–200 ns); tied to VDDI disables dead time and overlap protection |
| VDDA | High-side gate driver supply | 5–30 V supply for VOA output stage; independent UVLO (8 V) prevents high-side misfire during undervoltage |
| GNDA | High-side gate driver ground | Return path for VOA; isolated from GNDI and GNDB; requires separate layout plane for noise immunity |
| VDDB | Low-side gate driver supply | 5–30 V supply for VOB; independent UVLO (8 V) ensures safe low-side turn-off during supply sag |
| GNDB | Low-side gate driver ground | Return path for VOB; typically connected to system power ground; must be decoupled locally |
| VOA | High-side gate driver output | Voltage-mode output sourcing/sinking ±6 A; includes short-circuit clamp to VDDA and shutdown clamp to GNDA |
| VOB | Low-side gate driver output | Voltage-mode output sourcing/sinking ±6 A; includes identical clamping and fault protection as VOA |
| NC | No-connect terminal | Pins 12, 13, and 15 are unbonded - must remain floating; no routing or thermal pad connection permitted |
Key Features
| Feature | Design Value |
|---|---|
| Voltage Mode Drive | Enables predictable gate current control via external RG; eliminates need for current-sense feedback loops |
| Programmable Dead Time | Adjustable 17–200 ns delay via single resistor on DT pin - eliminates external timing ICs in half-bridge designs |
| Overlap Protection | Hardware-enforced immediate low-state on both outputs if PWM and EN simultaneously assert - prevents shoot-through |
| Independent UVLO Monitoring | Dedicated 4 V (VDDI) and 8 V (VDDA/VDDB) lockout with hysteresis - guarantees safe startup/shutdown sequencing |
| Thermal Shutdown | Auto-recovering 150 °C trigger (TSD+) with 140 °C reset (TSD–); pulls outputs weakly low until temperature stabilizes |
| AEC-Q100 Qualified | Grade 1 (–40 to +125 °C) qualification - meets automotive reliability, ESD (4 kV HBM), and lifetime requirements |
Applications
| Onboard EV Chargers | Industrial Motor Drives |
|---|---|
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in 11–22 kW EVSE units using SiC half-bridges. IC Role / Device Role / Timing Role: High-side/low-side gate driver controlling SiC MOSFETs in interleaved totem-pole PFC and CLLC resonant stages. Use Value: 6 kVRMS isolation and 200 kV/µs CMTI ensure robust operation across 1000 V DC bus transients; <5 ns skew enables precise ZVS timing. |
Use Scenario: Field-oriented control (FOC) of permanent magnet synchronous motors (PMSM) in HVAC and pump inverters. IC Role / Device Role / Timing Role: Isolated gate driver for 3-phase inverter leg pairs, synchronized to PWM timer outputs from MCU. Use Value: Programmable dead time prevents shoot-through during rapid load transients; AEC-Q100 qualification supports extended industrial service life. |
| Renewable Energy Inverters | Uninterruptible Power Supplies |
|
Use Scenario: Grid-tied solar string inverters with transformerless topologies requiring reinforced isolation and high efficiency. IC Role / Device Role / Timing Role: Dual-channel driver for high-frequency SiC half-bridges in DC/AC conversion stage with active neutral point clamping. Use Value: 6 A drive strength reduces external gate buffer count; 1500 VRMS working voltage meets IEC 62109 creepage requirements. |
Use Scenario: Online double-conversion UPS systems with battery backup, where reliability and fault tolerance are critical. IC Role / Device Role / Timing Role: Gate driver for IGBT-based inverter stage handling 400 V DC bus and 230 V AC output with fast overload response. Use Value: Independent UVLO per channel prevents partial failure; shutdown clamp ensures safe turn-off during AC loss events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side/low-side isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Silicon Labs SI8239AD-D-ISR | SOIC-16 NB, 4 A drive, 5 V UVLO (VDDI), no deglitch filter, same PWM+EN interface | Limited to 4 A output - insufficient for >10 kW SiC designs; lower CMTI (150 kV/µs) | Select when cost sensitivity outweighs peak drive requirement and CMTI margin is acceptable |
| Infineon 1EDF5673KXUMA1 | PG-DSO-16, 6 A drive, 3.3/5 V logic compatible, integrated Miller clamp, no DT pin | Fixed dead time (~100 ns); lacks programmability and overlap protection; different pinout | Choose when board space is constrained and fixed dead time suffices; requires layout redesign |
Compared with SI82E99AEE-IS3R, SI8239AD-D-ISR offers lower cost but reduced drive and noise immunity, while 1EDF5673KXUMA1 provides integrated Miller clamping but sacrifices dead time flexibility and requires PCB rework - SI82E99AEE-IS3R uniquely balances programmability, robustness, and automotive qualification in SOIC-16.
Availability
SI82E99AEE-IS3R is available at Aetrix Electronics and suitable for onboard EV chargers, industrial motor drives, renewable energy inverters, and uninterruptible power supplies requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant performance.
Supply support for SI82E99AEE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for automotive, industrial, and communications markets.
The Si82Ex family was developed specifically for high-reliability isolated gate driving in next-generation power converters using wide-bandgap semiconductors, emphasizing safety certification, timing precision, and thermal resilience.
FAQ
What is the function of the DT pin on the SI82E99AEE-IS3R?
The DT pin on the SI82E99AEE-IS3R programs dead time between VOA and VOB transitions using an external resistor to GND (10–110 kΩ), yielding 17–200 ns delay. Connecting DT to VDDI disables dead time and overlap protection, allowing universal dual-driver operation. This pin directly controls shoot-through prevention in half-bridge circuits without external logic.
Does the SI82E99AEE-IS3R support both SiC and GaN FETs?
Yes, the SI82E99AEE-IS3R supports SiC and GaN FETs through its ±6 A peak output drive, 5–30 V gate supply range, and voltage-mode architecture that enables precise gate resistor tuning for optimal dV/dt control and overshoot suppression. Its 200 kV/µs CMTI and <5 ns skew are specifically validated for wide-bandgap switching speeds.
How does the EN pin behave during VDDI undervoltage conditions?
When VDDI falls below its 3.5 V UVLO threshold, the SI82E99AEE-IS3R ignores the EN pin state and forces both VOA and VOB low regardless of EN logic level. Normal EN functionality resumes only after VDDI rises above 4 V and remains stable for tUVLO (typically <1 µs), ensuring fail-safe behavior during power-up/down sequences.
What safety certifications apply to the SI82E99AEE-IS3R?
The SI82E99AEE-IS3R carries UL 1577 recognition (6 kVRMS, 1 min), CSA 62368-1 and 60601-1 (2 MOPP), VDE 60747-17, and CQC GB4943.1 - all for reinforced insulation. These certifications validate its use in medical, industrial, and automotive systems requiring dual protection against electric shock and fire hazards.
Can the SI82E99AEE-IS3R operate with a 3.3 V logic input?
Yes, the SI82E99AEE-IS3R accepts 3.3 V logic inputs on its PWM and EN pins because its CMOS-compatible inputs have VIH(min) = 0.7 × VDDI and VIL(max) = 0.3 × VDDI. With VDDI ≥ 4.7 V (minimum for reliable 3.3 V high-level recognition), the device reliably interprets standard 3.3 V microcontroller outputs without level shifting.
SI82E99AEE-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82E99AEE-IS3R FAQ
1.How can I place an order for SI82E99AEE-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E99AEE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E99AEE-IS3R reliable?
The price and inventory of SI82E99AEE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E99AEE-IS3R is usually 5 days.
3.What payment methods are accepted for SI82E99AEE-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E99AEE-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E99AEE-IS3R?
SI82E99AEE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E99AEE-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E99AEE-IS3R?
For technical support, including SI82E99AEE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E99AEE-IS3R requirements.
6.How does Aetrix verify that SI82E99AEE-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82E99AEE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E99AEE-IS3R meets industry standards.
7.What is the process for return or replacement of SI82E99AEE-IS3R?
All SI82E99AEE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E99AEE-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E99AEE-IS3R part is unused and in its original packaging.
Return procedure for SI82E99AEE-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI82E99AEE-IS3R Tags
-
TLP152(TPL,E
Toshiba Semiconductor and Storage

-
HT0740LG-G
Microchip Technology

-
FOD8314TR2
onsemi

-
1EDI60N12AFXUMA1
Infineon Technologies

-
1EDB7275FXUMA1
Infineon Technologies

-
UCC5350MCDR
Texas Instruments

-
2EDB7259KXUMA1
Infineon Technologies

-
UCC5304DWVR
Texas Instruments

-
SI8261BBC-C-ISR
Skyworks Solutions Inc.

-
HT0440LG-G
Microchip Technology

-
HCPL-0302-500E
Broadcom Limited

-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
