Skyworks Solutions Inc. SI82E99BCE-IS3R
- Part No.:
- SI82E99BCE-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82E99BCE-IS3R.pdf
- Description:
- 6 KV 2-CHANNEL ISOLATED VALUE GA
- Quantity:
- Payment:

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Product details
Overview
SI82E99BCE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver with high-side/low-side configuration, 6 A peak output current per channel, <5 ns channel-to-channel skew, and 6 kVRMS reinforced isolation. It drives SiC/GaN FETs in half-bridge topologies for onboard chargers and motor inverters.
For engineers reviewing the SI82E99BCE-IS3R datasheet, SI82E99BCE-IS3R pinout, SI82E99BCE-IS3R application, or SI82E99BCE-IS3R equivalent, key selection criteria include its EN-controlled enable logic, programmable dead time via DT pin, UVLO thresholds (4/8/12/15 V options), CMTI >200 kV/µs, and narrow-body SOIC-16 automotive-grade packaging.
Technical Context
The SI82E99BCE-IS3R implements capacitive silicon-dioxide isolation with differential RF-modulated OOK signaling, enabling precise timing control and fault tolerance between input and outputs. Its architecture supports independent UVLO monitoring per supply rail (VDDI, VDDA, VDDB) and integrates thermal shutdown with hysteresis (TSD+ = 150 °C, TSD– = 135 °C).
This device uses voltage-mode drive with external gate resistors to tune switching speed and overshoot. The DT pin accepts a resistor (10–110 kΩ) to set dead time (tDT = 1.73 × RDT + 5.74 ns), and overlap protection forces both outputs low during simultaneous high inputs to prevent shoot-through.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6 kVRMS for 1 minute (UL 1577, VDE 60747-17, CSA 62368-1) |
| Channel-to-Channel Skew | <5 ns - ensures synchronized switching in half-bridge legs |
| Peak Output Current | 6 A sourcing/sinking - drives high-Qg SiC/GaN FETs without external buffers |
| CMTI | >200 kV/µs - maintains signal integrity in noisy high-dV/dt power stages |
| Input Supply Range | 3–20 V - compatible with 3.3 V, 5 V, and 15 V controller logic |
| Gate Supply Range | 5–30 V - supports 12 V and 15 V gate bias for IGBTs/SiC FETs |
| Operating Temperature | –40 to +125 °C - qualified per AEC-Q100 Grade 1 for automotive use |
Pinout & Package
Narrow-body 16-pin SOIC package (SOIC-16 NB) with creepage ≥8.3 mm and clearance ≥8.0 mm; RoHS-compliant, automotive-grade molding compound.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 VIA | Non-inverting logic input for channel A | Accepts CMOS-level PWM or control signal; deglitched on select variants |
| 2 VDDA | Gate driver A power supply | 5–30 V input; monitored by independent UVLO (threshold depends on variant) |
| 3 VOA | Gate driver A output | 6 A peak sourcing/sinking; includes short-circuit clamp to VDDA |
| 4 GNDA | Gate driver A ground reference | Functional isolation barrier separates GNDA from GNDI and GNDB |
| 5 VDDB | Gate driver B power supply | 5–30 V input; independently monitored UVLO |
| 6 VOB | Gate driver B output | 6 A peak sourcing/sinking; short-circuit clamp to VDDB |
| 7 GNDB | Gate driver B ground reference | Isolated from GNDA and GNDI; enables floating high-side operation |
| 8 VDDI | Logic input power supply | 3–20 V; powers internal isolator and logic; UVLO threshold configurable |
| 9 VIB | Non-inverting logic input for channel B | CMOS-compatible; matches VIA timing for matched propagation delay |
| 10 GNDI | Logic input ground | Reference for VIA, VIB, EN, DT; galvanically isolated from GNDA/GNDB |
| 11 DT | Dead time programming input | Resistor-to-GND sets dead time; tied to VDDI disables dead time and overlap |
| 12 EN | Active-high enable input | Drives VOA/VOB low when deasserted; tEID = 25 ns max resume delay |
| 13 NC | No connection | Not bonded; must remain unconnected per design |
| 14 NC | No connection | Not bonded; must remain unconnected per design |
| 15 NC | No connection | Not bonded; must remain unconnected per design |
| 16 VDDI | Secondary logic supply pin | Redundant VDDI connection for improved PSRR and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Voltage Mode Drive | External gate resistors directly control dV/dt, EMI, and overshoot without complex loop compensation |
| Programmable Dead Time | 10–110 kΩ resistor on DT pin sets 22–192 ns dead time; prevents shoot-through in half-bridges |
| Overlap Protection | Simultaneous high inputs on VIA/VIB force immediate VOA/VOB low - hardware-level fault containment |
| Shutdown Clamp | Active pull-down to GNDA/GNDB when VDDA/VDDB unpowered - eliminates parasitic turn-on risk |
| AEC-Q100 Qualified | Grade 1 (–40 to +125 °C) qualification with automotive-specific process flow and defectivity controls |
| UVLO Flexibility | Four factory-set thresholds (4/8/12/15 V) per supply rail - matches diverse gate bias and controller requirements |
Applications
| Onboard Charger (OBC) | Motor Inverter |
|---|---|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV charging systems with SiC MOSFETs operating at 100–200 kHz. IC Role / Device Role / Timing Role: High-side/low-side isolated gate driver controlling half-bridge legs in totem-pole PFC and DC-DC stages. Use Value: 6 kVRMS isolation and 200 kV/µs CMTI ensure reliable operation across 1000 V bus transients; <5 ns skew enables precise ZVS control. |
Use Scenario: Traction inverter stage driving 650 V/1200 V SiC modules in 400 V/800 V battery architectures. IC Role / Device Role / Timing Role: Dual isolated driver providing independent gate control with programmable dead time for phase-leg switching. Use Value: 6 A drive strength reduces external buffer need; AEC-Q100 qualification supports ASIL-B system integration. |
| Industrial UPS | Grid-Tied Solar Inverter |
Use Scenario: Double-conversion UPS with IGBT-based inverter stage requiring robust isolation and fast fault response. IC Role / Device Role / Timing Role: Isolated gate driver enabling high-efficiency 16 kHz switching with thermal shutdown and UVLO monitoring. Use Value: Integrated shutdown clamp prevents false turn-on during brownout; 1500 VRMS working voltage meets IEC 62109 creepage requirements. |
Use Scenario: Transformerless string inverters using SiC FETs in H5 and H6 topologies with bipolar 1000 V DC link. IC Role / Device Role / Timing Role: Reinforced-isolation driver delivering independent high-side/low-side control with overlap protection. Use Value: 10 kV bipolar surge rating withstands lightning-induced transients; universal pinout supports both H5 and full-bridge layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239BD-IS3R | Same SOIC-16 NB package and Si82Ex family architecture, but uses DIS (disable) instead of EN (enable) logic; identical isolation, skew, and drive specs | Requires inverted control signal polarity for safety shutdown; no change in half-bridge timing behavior or layout | Select when system controller asserts active-high disable rather than enable; pin-compatible with same PCB footprint |
| UCC5390SCDR | Texas Instruments part with 5.7 A peak drive, 5 kVRMS isolation, and 100 kV/µs CMTI; different pinout (SOIC-16 WB), no integrated overlap protection | Lacks hardware overlap protection - requires external logic or MCU coordination to avoid shoot-through | Choose for cost-sensitive industrial designs where overlap control is handled at controller level; verify layout compatibility due to wide-body SOIC |
Compared with SI82E99BCE-IS3R, Si8239BD-IS3R offers identical performance with inverted enable polarity, while UCC5390SCDR trades overlap protection and higher CMTI for lower cost and different packaging - making SI82E99BCE-IS3R optimal for automotive and high-reliability half-bridge systems requiring hardware-enforced shoot-through prevention.
Availability
SI82E99BCE-IS3R is available at Aetrix Electronics and suitable for onboard chargers, motor inverters, and industrial UPS systems requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for SI82E99BCE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si82Ex family was designed specifically for high-reliability isolated gate driving in electric vehicle powertrain, renewable energy, and industrial motor control - emphasizing safety certification, timing precision, and ruggedness across temperature and voltage extremes.
FAQ
What is the isolation architecture used in the SI82E99BCE-IS3R?
The SI82E99BCE-IS3R uses capacitive silicon-dioxide (SiO₂) isolation with differential RF-modulated OOK signaling across two high-voltage capacitors. This architecture delivers 6 kVRMS reinforced isolation, >200 kV/µs CMTI, and <5 ns channel-to-channel skew - all verified per UL, VDE, and CSA safety standards. Unlike optocouplers, it provides stable timing over temperature and lifetime.
Does the SI82E99BCE-IS3R support both high-side/low-side and dual independent configurations?
The SI82E99BCE-IS3R is configured exclusively as a high-side/low-side driver with PWM input (pin 1 = VIA, pin 9 = VIB, pin 1 = PWM per datasheet Figure 15). It does not support universal dual-independent mode - that functionality is reserved for Si82E29x/Si82E39x variants. Its DT pin enables dead time insertion and overlap protection specific to half-bridge operation.
What UVLO thresholds are implemented in the SI82E99BCE-IS3R?
The SI82E99BCE-IS3R features factory-configured UVLO thresholds: 4 V (±0.2 V) on VDDI, 8 V (±0.3 V) on VDDA, and 12 V (±0.3 V) on VDDB. These values are fixed per ordering code and cannot be adjusted externally. Each rail has independent monitoring - if VDDA drops below 7.7 V, VOA is forced low regardless of VDDI or VDDB status.
How is dead time programmed on the SI82E99BCE-IS3R?
Dead time on the SI82E99BCE-IS3R is set by connecting a resistor (RDT) between pin 11 (DT) and GNDI. Using Equation tDT = 1.73 × RDT + 5.74 ns (with RDT in kΩ), a 47 kΩ resistor yields ~87 ns typical dead time. Connecting DT to VDDI disables dead time and overlap protection, forcing dual-driver behavior - though this is not the intended mode for SI82E99x devices.
Is the SI82E99BCE-IS3R pin-compatible with other Si82Ex variants?
The SI82E99BCE-IS3R shares the same narrow-body SOIC-16 (NB) package and pinout with Si82E89BCE-IS3R and Si82E29BCE-IS3R, but differs in input configuration: SI82E99x uses PWM + VIB, while SI82E29x uses VIA + VIB. EN pin (12) is common to SI82E39x/SI82E99x; DIS pin (12) is used in SI82E29x/SI82E89x - requiring firmware or logic-level adaptation for direct substitution.
SI82E99BCE-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82E99BCE-IS3R FAQ
1.How can I place an order for SI82E99BCE-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82E99BCE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82E99BCE-IS3R reliable?
The price and inventory of SI82E99BCE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82E99BCE-IS3R is usually 5 days.
3.What payment methods are accepted for SI82E99BCE-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82E99BCE-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82E99BCE-IS3R?
SI82E99BCE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82E99BCE-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82E99BCE-IS3R?
For technical support, including SI82E99BCE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82E99BCE-IS3R requirements.
6.How does Aetrix verify that SI82E99BCE-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82E99BCE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82E99BCE-IS3R meets industry standards.
7.What is the process for return or replacement of SI82E99BCE-IS3R?
All SI82E99BCE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82E99BCE-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82E99BCE-IS3R part is unused and in its original packaging.
Return procedure for SI82E99BCE-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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