Skyworks Solutions Inc. SI82F29AEE-IS3R
- Part No.:
- SI82F29AEE-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82F29AEE-IS3R.pdf
- Description:
- 6 KV 2-CHANNEL ISOLATED SELVCD G
- Quantity:
- Payment:

- Shipping:

Inventory:3,103
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI82F29AEE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver in narrow-body 16-pin SOIC package, configured as a universal (independent input) driver with disable (DIS) control, 8-V UVLO, and SelVCD™ current drive. It delivers ≤5 ns channel-to-channel skew, 200 kV/μs CMTI, and 6 kVRMS isolation for driving SiC/GaN FETs in half-bridge motor inverters.
For engineers reviewing the SI82F29AEE-IS3R datasheet, SI82F29AEE-IS3R pinout, SI82F29AEE-IS3R application, or SI82F29AEE-IS3R equivalent, key selection criteria include its DIS-enabled universal configuration, SPD± programmable sourcing/sinking current (8 levels), integrated Miller clamp, dead time programmability via external resistor, and AEC-Q100 qualification for automotive powertrain systems.
Technical Context
The SI82F29AEE-IS3R implements capacitive digital isolation using dual SiO₂ barriers with RF OOK modulation, enabling precise timing and fault-tolerant signal transfer. Its logic inputs are CMOS-compatible with deglitch filtering, and outputs operate as regulated current sources-not voltage sources-enabling direct gate connection without external resistors.
It features independent UVLO monitoring on VDDI (8 V threshold), VDDA, and VDDB, with defined low-state outputs during any supply undervoltage condition. The DIS pin forces both VOA and VOB low unconditionally when high, with tDID < 40 ns propagation delay to shutdown and tEID < 60 ns to resume operation after deassertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 6 kVRMS for 1 minute - meets reinforced insulation requirements per UL 1577, VDE 60747-17, and CSA 62368-1. |
| Channel Skew | <5 ns - ensures precise synchronous switching of high-side and low-side FETs in half-bridge topologies. |
| CMTI | >200 kV/μs - prevents false triggering in noisy high-dV/dt environments like SiC/GaN-based inverters. |
| UVLO Threshold | 8 V on VDDI - guarantees clean startup/shutdown behavior and avoids partial turn-on of power devices. |
| Operating Temp | –40 °C to +125 °C - supports under-hood automotive and industrial motor drive applications. |
| Input Supply Range | 3 V to 20 V - compatible with 3.3 V, 5 V, and 12 V logic controllers without level shifting. |
| Gate Supply Range | 5 V to 30 V - enables direct drive of 12 V and 15 V gate supplies for IGBTs, SiC, and GaN FETs. |
| Output Current | Programmable 8-level sourcing/sinking (SPD±) - eliminates gate resistors and enables dynamic slew rate control. |
Pinout & Package
Narrow-body 16-pin SOIC (NB SOIC-16) package with 1.27 mm pitch, creepage ≥8.0 mm, clearance ≥7.5 mm, and reinforced insulation barrier between input and output sides.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for driver A | Direct CMOS-compatible control of VOA; active-high, deglitched, Schmitt-triggered. |
| VIB | Non-inverting logic input for driver B | Direct CMOS-compatible control of VOB; independent of VIA, enabling universal dual-driver operation. |
| DIS | Active-high disable control | Forces VOA and VOB low regardless of VIA/VIB state; used for system-level fault shutdown. |
| DT | Dead time programming input | Resistor-to-GND sets dead time (10–110 kΩ → ~20–120 ns); connect to VDDI to disable dead time/overlap protection. |
| SPD+ | Sourcing current programming input | Resistor-to-GND selects one of eight turn-on current levels (SPD1–SPD8); enables Miller clamp optimization. |
| SPD− | Sinking current programming input | Resistor-to-GND selects one of eight turn-off current levels; activates Miller clamp during VOH→VOL transition. |
| VDDI | Logic input supply | 3–20 V supply powering input circuitry and isolation modulator; monitored by 8-V UVLO. |
| GNDI | Logic input ground | Reference for all digital inputs (VIA, VIB, DIS, DT, SPD±); galvanically isolated from GNDA/GNDB. |
| VDDA / GNDA | Driver A gate supply and ground | 5–30 V isolated supply for VOA output stage; GNDA is local return, not connected to GNDI. |
| VDDB / GNDB | Driver B gate supply and ground | 5–30 V isolated supply for VOB output stage; GNDB is local return, independent of GNDA. |
| VOA / VOB | Gate driver outputs | Current-source outputs with integrated Miller clamp; no external gate resistors required. |
| NC (Pins 12,13) | No-connect terminals | Not bonded; must remain unconnected to avoid parasitic coupling or ESD path disruption. |
Key Features
| Feature | Design Value |
|---|---|
| Selectable Variable Current Drive (SelVCD™) | Eight discrete sourcing/sinking current levels set via SPD± resistors - replaces gate resistors and enables adaptive switching speed. |
| Integrated Miller Clamp | Automatically engages during VOH→VOL transition when VOA/B falls below VMCTA/B - suppresses Miller-induced shoot-through without external components. |
| Programmable Dead Time | External resistor on DT pin sets dead time (20–120 ns typical); disabled by tying DT to VDDI for universal dual-driver use. |
| AEC-Q100 Qualified | Grade 1 (–40 °C to +125 °C) qualification - validated for automotive powertrain, onboard chargers, and traction inverters. |
| Defined Output States | No floating or unknown outputs under UVLO, power loss, or DIS assertion - VOA/VOB driven low with shutdown clamp. |
| High CMTI & Low Skew | 200 kV/μs common-mode transient immunity and <5 ns channel-to-channel skew - critical for fast-switching SiC/GaN systems. |
Applications
| Motor Drives | Onboard Chargers (OBC) |
|---|---|
|
Use Scenario: Three-phase inverter driving PMSM or induction motors in EV traction or industrial servo systems. IC Role / Device Role / Timing Role: Universal dual gate driver controlling high-side and low-side switches per phase leg with independent VIA/VIB inputs and DIS-fault response. Use Value: ≤5 ns skew and 200 kV/μs CMTI ensure precise commutation timing and noise immunity in high-power, high-dV/dt motor phases. |
Use Scenario: Bidirectional AC/DC and DC/DC conversion in automotive 11 kW+ OBC modules. IC Role / Device Role / Timing Role: Isolated gate driver for SiC MOSFET half-bridges in totem-pole PFC and CLLC resonant stages. Use Value: SPD± programmable current drive enables optimized dV/dt control during zero-voltage switching transitions, reducing EMI. |
| Power Inverters | Uninterruptible Power Supplies |
|
Use Scenario: Solar string inverters and energy storage system (ESS) inverters operating at >100 kHz switching frequency. IC Role / Device Role / Timing Role: High-reliability isolated driver for SiC FETs in H-bridge and multilevel topologies with DIS-based system fault coordination. Use Value: 6 kVRMS isolation and 1500 VRMS working voltage meet reinforced insulation requirements for grid-tied equipment safety standards. |
Use Scenario: Online double-conversion UPS delivering clean 50/60 Hz output with fast transfer and harmonic suppression. IC Role / Device Role / Timing Role: Gate driver for IGBTs or SiC FETs in inverter stage, coordinated via DIS signal with battery management and rectifier control. Use Value: AEC-Q100 qualification and –40 °C to +125 °C operation support extended field life in telecom and datacenter UPS deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si82F39AEE-IS3R | Same NB SOIC-16 package and SelVCD™, but uses EN (enable) instead of DIS (disable) logic polarity. | Requires inverted control signal for fault shutdown; lacks DIS's unconditional low-state assertion on high input. | Select when system controller natively provides active-high enable rather than active-high disable signals. |
| UCC5390SCD | TI device with 5.7 kVRMS isolation, 35 V max VDD, and fixed 4-A peak output - no SPD± programmability or Miller clamp. | Relies on external gate resistors and lacks dynamic slew control; requires additional components for Miller suppression. | Choose for cost-sensitive non-automotive applications where fixed drive strength suffices and design simplicity is prioritized. |
Compared with SI82F29AEE-IS3R, Si82F39AEE-IS3R offers identical isolation and timing specs but differs in control polarity, while UCC5390SCD trades programmability and integrated protection for lower BOM count in less demanding topologies.
Availability
SI82F29AEE-IS3R is available at Aetrix Electronics and suitable for automotive onboard chargers, industrial motor drives, and renewable energy inverters requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant isolation performance.
Supply support for SI82F29AEE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.
The Si82Fx family was designed specifically for next-generation power conversion systems using wide-bandgap semiconductors, emphasizing ultra-low skew, programmable drive strength, and automotive-grade robustness in isolated gate drive.
FAQ
What is the function of the DIS pin on the SI82F29AEE-IS3R?
The DIS (Disable) pin on the SI82F29AEE-IS3R is an active-high control input that unconditionally forces both VOA and VOB outputs low when asserted, regardless of the states of VIA, VIB, or power supply conditions. This provides deterministic fault shutdown for system-level protection. The SI82F29AEE-IS3R exits disable mode within tEID < 60 ns after DIS falls below VIH, ensuring rapid recovery. Unlike EN-based variants, DIS guarantees immediate low-state enforcement without dependency on input supply sequencing.
Does the SI82F29AEE-IS3R require external gate resistors?
No, the SI82F29AEE-IS3R does not require external gate resistors due to its Selectable Variable Current Drive (SelVCD™) architecture and integrated Miller clamp. Its VOA and VOB outputs operate as tightly regulated current sources across eight programmable levels (set via SPD± pins), eliminating gate resistor dependency for slew rate control. Adding external gate resistors degrades Miller clamp effectiveness and increases switching losses - Skyworks explicitly advises against them in the datasheet to maintain optimal performance and thermal safety.
What isolation certifications apply to the SI82F29AEE-IS3R?
The SI82F29AEE-IS3R is certified for 6 kVRMS isolation per UL 1577 (1-minute test), reinforced insulation per VDE 60747-17 and CSA 62368-1, and 2 MOPP per IEC 60601-1. It achieves 1500 VRMS working voltage and withstands 10 kV bipolar surge. These ratings are validated through Skyworks' proprietary silicon dioxide capacitive isolation technology - not optocoupler-based - and support safety-critical applications including automotive traction inverters and medical-grade power supplies.
How is dead time programmed on the SI82F29AEE-IS3R?
Dead time on the SI82F29AEE-IS3R is programmed using an external resistor (RDT) connected between the DT pin and GNDI. RDT values from 10 kΩ to 110 kΩ yield typical dead times of 20 ns to 120 ns, calculated as tDT = 1.73 × RDT + 5.74 (ns). A 0.1 µF ceramic capacitor placed near the DT pin improves noise immunity. To disable dead time and overlap protection - converting the device to a pure dual driver - connect DT directly to VDDI, as confirmed in the functional block diagram and truth table for Si82F29x universal configuration.
Is the SI82F29AEE-IS3R qualified for automotive applications?
Yes, the SI82F29AEE-IS3R is AEC-Q100 qualified (Grade 1, –40 °C to +125 °C) and built using automotive-specific manufacturing flows for low defectivity and long-term reliability. It supports automotive applications including onboard chargers, DC-DC converters, and traction inverters. Its 6 kVRMS isolation, 200 kV/μs CMTI, and DIS-based fault response meet functional safety requirements for ASIL-B systems when integrated into properly architected control schemes - though full ASIL certification requires system-level validation beyond the component level.
SI82F29AEE-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82F29AEE-IS3R FAQ
1.How can I place an order for SI82F29AEE-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82F29AEE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82F29AEE-IS3R reliable?
The price and inventory of SI82F29AEE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82F29AEE-IS3R is usually 5 days.
3.What payment methods are accepted for SI82F29AEE-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82F29AEE-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82F29AEE-IS3R?
SI82F29AEE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82F29AEE-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82F29AEE-IS3R?
For technical support, including SI82F29AEE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82F29AEE-IS3R requirements.
6.How does Aetrix verify that SI82F29AEE-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82F29AEE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82F29AEE-IS3R meets industry standards.
7.What is the process for return or replacement of SI82F29AEE-IS3R?
All SI82F29AEE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82F29AEE-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82F29AEE-IS3R part is unused and in its original packaging.
Return procedure for SI82F29AEE-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI82F29AEE-IS3R Tags
-
TLP152(TPL,E
Toshiba Semiconductor and Storage

-
HT0740LG-G
Microchip Technology

-
FOD8314TR2
onsemi

-
1EDI60N12AFXUMA1
Infineon Technologies

-
1EDB7275FXUMA1
Infineon Technologies

-
UCC5350MCDR
Texas Instruments

-
2EDB7259KXUMA1
Infineon Technologies

-
UCC5304DWVR
Texas Instruments

-
SI8261BBC-C-ISR
Skyworks Solutions Inc.

-
HT0440LG-G
Microchip Technology

-
HCPL-0302-500E
Broadcom Limited

-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
