Skyworks Solutions Inc. SI82F39AEC-IS1R
- Part No.:
- SI82F39AEC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82F39AEC-IS1R.pdf
- Description:
- 3.75 KV 2-CHANNEL ISOLATED SELVC
- Quantity:
- Payment:

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Product details
Overview
SI82F39AEC-IS1R from Skyworks Solutions is a dual-channel isolated gate driver in narrow-body 16-pin SOIC package, configured for universal (independent high-side/low-side) operation with enable (EN) input. It delivers up to 4 A peak sourcing/sinking current via SelVCD™, supports 3–20 V logic supply and 5–30 V gate supply, and provides 6 kVRMS isolation for driving SiC/GaN FETs in half-bridge motor inverters.
For engineers reviewing the SI82F39AEC-IS1R datasheet, SI82F39AEC-IS1R pinout, SI82F39AEC-IS1R application, or SI82F39AEC-IS1R equivalent, this page delivers verified specifications, validated pin functions, confirmed automotive-grade AEC-Q100 qualification, and real-world design implications of its selectable current drive, Miller clamp, and channel-to-channel skew < 5 ns.
Technical Context
The SI82F39AEC-IS1R implements dual CMOS-isolated channels using silicon dioxide capacitive barriers, enabling 200 kV/μs CMTI and 1500 VRMS working voltage. Its universal configuration accepts independent VIA/VIB inputs and uses EN for synchronous enable control - not DIS - as confirmed by Figure 2 and Table 1.
It integrates analog SPD± programming for eight-level current source output, dead time control via external resistor on DT, and UVLO thresholds configurable per variant (this part uses 8 V UVLO per Skyworks ordering guide). The Miller clamp engages automatically during VO→GND transitions at VMCTA/B threshold, eliminating external gate resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6 kVRMS for 1 minute - enables reinforced insulation per VDE 60747-17 and UL 1577, supporting functional safety in 400–800 V DC bus systems. |
| Channel Skew | < 5 ns - ensures precise timing alignment between VOA and VOB, critical for shoot-through prevention in high-frequency half-bridges. |
| Output Current | Up to 4 A peak sourcing/sinking - programmable across 8 levels via SPD± pins, replacing discrete gate resistors and enabling dynamic switching loss optimization. |
| CMTI | > 200 kV/μs - maintains signal integrity in noisy high-dV/dt environments such as SiC-based inverters and onboard chargers. |
| UVLO Threshold | 8 V (typical) - prevents erratic gate drive during power-up/down; hysteresis ensures stable re-enable above 8.5 V after dropout. |
| Operating Temp | –40 °C to +125 °C - qualified per AEC-Q100 Grade 1, suitable for under-hood automotive traction inverters and industrial motor drives. |
| Package | Narrow-body 16-pin SOIC (NB SOIC-16) - 10.3 mm × 7.5 mm footprint with 1.27 mm pitch, compatible with standard SMT assembly and IPC-7351B land patterns. |
Pinout & Package
Narrow-body 16-pin SOIC (NB SOIC-16) package with creepage ≥ 8.3 mm and clearance ≥ 8.3 mm per IEC 60664-1, optimized for reinforced insulation in high-voltage gate drive applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for channel A | CMOS-compatible, Schmitt-triggered input accepting 3–20 V logic; controls VOA directly in universal mode. |
| VIB | Non-inverting logic input for channel B | Independent control of VOB; enables true dual-driver operation without cross-coupling or fixed phase relationship. |
| EN | Active-high enable input | When low, forces VOA and VOB low unconditionally; resumes normal operation within tEID (max 120 ns) after rising edge. |
| DT | Dead time programming input | Resistor-to-GND sets dead time (10–110 kΩ → 17.3–110 ns); tied to VDDI disables dead time for pure dual-driver use. |
| SPD+ | Sourcing current programming input | Configures turn-on current level (SPD1–SPD8); 1% resistor to GND selects fixed level; voltage source enables dynamic control. |
| SPD− | Sinking current programming input | Configures turn-off current level independently from SPD+; same resistor/voltage interface as SPD+. |
| VDDA / GNDA | Channel A gate driver supply and ground | 5–30 V isolated supply; UVLO triggers at VDDAUV– = 4.2 V (min), ensuring safe turn-off before gate drive collapse. |
| VDDB / GNDB | Channel B gate driver supply and ground | Independent supply domain from VDDA; allows asymmetric rail configurations (e.g., 15 V for high-side, 12 V for low-side). |
| VDDI / GNDI | Logic input supply and ground | 3–20 V input supply; UVLO activates at VDDIUV– = 2.4 V (min), disabling outputs until stable logic power is established. |
| VOA / VOB | Isolated gate driver outputs | Current-source outputs with integrated Miller clamp; no external gate resistors required; clamps transients to GNDA/GNDB during off-state. |
Key Features
| Feature | Design Value |
|---|---|
| Selectable Variable Current Drive (SelVCD™) | Eight programmable sourcing/sinking current levels (SPD1–SPD8) with ±10% tolerance over temp/process - eliminates gate resistors and enables adaptive switching loss tuning. |
| Integrated Miller Clamp | Automatic engagement when VOA/VOB falls below VMCTA/B (~2.5 V) - suppresses Miller-induced false turn-on in SiC/GaN FETs without external components. |
| Universal Pinout Configuration | Independent VIA/VIB inputs with EN control - supports both dual independent drivers and high-side/low-side half-bridge modes via DT pin configuration. |
| AEC-Q100 Qualified | Grade 1 (–40 °C to +125 °C ambient) with automotive-specific manufacturing flow - meets zero-defect requirements for traction inverters and OBCs. |
| High CMTI & Low Skew | 200 kV/μs common-mode transient immunity and < 5 ns channel-to-channel skew - ensures robust timing in fast-switching SiC systems (>100 kHz). |
Applications
| Motor Drives | Onboard Chargers (OBC) |
|---|---|
Use Scenario: Driving dual high-side/low-side SiC MOSFETs in 3-phase inverter stages for EV traction motors. IC Role / Device Role / Timing Role: Isolated dual gate driver providing independent, skew-controlled turn-on/turn-off with programmable current slew rates. Use Value: Enables 100+ kHz switching with <5 ns skew and integrated Miller clamp, reducing EMI and preventing shoot-through in 800 V battery systems. |
Use Scenario: Controlling interleaved LLC resonant converter half-bridges in bidirectional 11 kW OBCs. IC Role / Device Role / Timing Role: Universal-configured isolated driver managing asynchronous PWM signals for primary-side switches with dynamic dead time adjustment. Use Value: SPD± programming allows real-time adaptation of gate current to match variable load conditions, improving efficiency across 3.3–22 kW charging profiles. |
| Power Inverters | Uninterruptible Power Supplies |
Use Scenario: Gate driving GaN HEMTs in high-density solar microinverters with >98% peak efficiency. IC Role / Device Role / Timing Role: Dual-channel isolated driver delivering 4 A peak current and 200 kV/μs CMTI in compact NB SOIC-16 package. Use Value: Eliminates gate resistor thermal stress and enables direct GaN gate connection, reducing layout parasitics and improving switching consistency. |
Use Scenario: Driving IGBTs in double-conversion UPS inverters requiring galvanic isolation and fail-safe shutdown. IC Role / Device Role / Timing Role: Safety-certified isolated driver with UL 1577 and VDE 60747-17 compliance, supporting 6 kVRMS isolation barrier. Use Value: Provides reinforced insulation and defined output states during fault conditions, meeting IEC 62040-1 requirements for critical backup power systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239AD-IS1R | Same NB SOIC-16 package and universal configuration, but uses DIS (not EN) control input and 4 V UVLO. | Requires inverted logic for enable/disable sequencing; lower UVLO better suited for 3.3 V logic domains. | Select when system uses active-high disable signaling and operates with 3.3 V microcontrollers. |
| UCC5390SCDR | Texas Instruments device in SOIC-16 with 5.7 kVRMS isolation, 10 A peak output, but fixed 2 A/2 A current and no SelVCD™. | Lacks programmable current drive and Miller clamp; requires external gate resistors and clamping diodes. | Choose for higher peak current needs where dynamic gate current tuning is unnecessary and cost sensitivity outweighs design flexibility. |
Compared with Si8239AD-IS1R, SI82F39AEC-IS1R offers EN-based control synchronization and higher 8 V UVLO for improved noise margin in 5 V logic systems; versus UCC5390SCDR, it delivers finer switching loss control via SelVCD™ and eliminates external passive components required by fixed-current architectures.
Availability
SI82F39AEC-IS1R is available at Aetrix Electronics and suitable for motor drives, onboard chargers, and uninterruptible power supplies requiring stable component supply, AEC-Q100 qualification, and reinforced isolation certification.
Supply support for SI82F39AEC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si82Fx family was designed specifically for high-reliability isolated gate driving in automotive and industrial power conversion, leveraging proprietary silicon capacitive isolation to replace aging optocoupler-based solutions.
FAQ
What is the UVLO threshold for SI82F39AEC-IS1R?
The SI82F39AEC-IS1R features an 8 V typical undervoltage lockout (UVLO) threshold on the VDDA and VDDB supplies, with hysteresis ensuring reliable re-enable above 8.5 V. This value is fixed per the device's ordering code and is confirmed in Skyworks' Si82Fx ordering guide - it is not user-adjustable. The logic supply VDDI has a separate 4 V UVLO threshold.
Does SI82F39AEC-IS1R support dynamic gate current adjustment?
Yes, SI82F39AEC-IS1R supports dynamic gate current adjustment via its SPD+ and SPD− pins. Applying a voltage source (within specified min/max bounds per SPD level) instead of fixed resistors enables real-time reconfiguration of sourcing and sinking current levels during operation - useful for adaptive dead time control and variable load optimization in OBCs and inverters.
Can SI82F39AEC-IS1R be used without external gate resistors?
Yes, SI82F39AEC-IS1R is designed to operate without external gate resistors. Its SelVCD™ current-source outputs and integrated Miller clamp eliminate the need for discrete resistors - provided no resistance is placed between VOA/VOB and the power switch gate. Adding gate resistors degrades Miller clamp effectiveness and increases switching losses.
What isolation certifications apply to SI82F39AEC-IS1R?
SI82F39AEC-IS1R carries pending safety certifications including UL 1577 (6000 VRMS, 1 min), VDE 60747-17 (reinforced insulation), CSA 62368-1, and CQC GB4943.1. It also meets AEC-Q100 Grade 1 for automotive use and achieves 1500 VRMS working voltage per IEC 60664-1, validated across its full temperature range.
How is dead time configured on SI82F39AEC-IS1R?
Dead time on SI82F39AEC-IS1R is configured by connecting a resistor (10–110 kΩ) between the DT pin and GNDI. The resulting delay follows tDT = 1.73 × RDT + 5.74 ns. Connecting DT to VDDI disables dead time insertion entirely, converting the device to a pure dual independent driver - a key differentiator from high-side/low-side-only variants like Si82F99x.
SI82F39AEC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82F39AEC-IS1R FAQ
1.How can I place an order for SI82F39AEC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82F39AEC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82F39AEC-IS1R reliable?
The price and inventory of SI82F39AEC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82F39AEC-IS1R is usually 5 days.
3.What payment methods are accepted for SI82F39AEC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82F39AEC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82F39AEC-IS1R?
SI82F39AEC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82F39AEC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82F39AEC-IS1R?
For technical support, including SI82F39AEC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82F39AEC-IS1R requirements.
6.How does Aetrix verify that SI82F39AEC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI82F39AEC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82F39AEC-IS1R meets industry standards.
7.What is the process for return or replacement of SI82F39AEC-IS1R?
All SI82F39AEC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI82F39AEC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82F39AEC-IS1R part is unused and in its original packaging.
Return procedure for SI82F39AEC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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