Skyworks Solutions Inc. SI82F39AEE-IS3R
- Part No.:
- SI82F39AEE-IS3R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82F39AEE-IS3R.pdf
- Description:
- 6 KV 2-CHANNEL ISOLATED SELVCD G
- Quantity:
- Payment:

- Shipping:

Inventory:2,506
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI82F39AEE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver with Universal configuration, CMOS inputs, and Selectable Variable Current Drive (SelVCD™) for driving SiC/GaN FETs and IGBTs in half-bridge topologies. It delivers 6 kVRMS isolation, <5 ns channel-to-channel skew, 200 kV/μs CMTI, and programmable dead time via external resistor on DT pin. Used in onboard chargers and motor drives requiring high reliability and Miller clamping.
For engineers reviewing the SI82F39AEE-IS3R datasheet, SI82F39AEE-IS3R pinout, SI82F39AEE-IS3R application, or SI82F39AEE-IS3R equivalent, this page provides verified functional identity, validated pin mapping for SOIC-16 narrow-body package, confirmed SelVCD™ current levels, UVLO thresholds, and real-world design implications of SPD± programming and Miller clamp behavior - all derived from Skyworks' official preliminary datasheet (206821A, May 2024).
Technical Context
The SI82F39AEE-IS3R implements dual-channel capacitive isolation using differential RF-modulated OOK signaling across silicon dioxide barriers, enabling 6 kVRMS reinforced insulation and 1500 VRMS working voltage. Its Universal configuration supports independent control of VOA and VOB via VIA and VIB inputs, with EN enable logic and DT-programmable dead time.
It integrates SelVCD™ as a precision current source (±10% tolerance over temp/process for 8/12/15 V UVLO variants), Miller clamp triggered at VMCTA/B threshold during VOH→VOL transitions, and independent UVLO monitoring on VDDI, VDDA, and VDDB rails - each with configurable thresholds (4/8/12/15 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6 kVRMS for 1 minute - meets UL 1577, VDE 60747-17, and CSA 62368-1 reinforced insulation requirements. |
| Channel Skew | <5 ns - enables precise timing alignment between high-side and low-side gate drive signals in half-bridge circuits. |
| CMTI | >200 kV/μs - ensures robust noise immunity in high-dV/dt environments like SiC/GaN inverters. |
| Input Supply Range | 3 V to 20 V - supports direct interface with MCU GPIOs, FPGA outputs, or level-shifted control logic without external regulators. |
| Gate Supply Range | 5 V to 30 V - accommodates wide-range bias supplies for diverse power switches including 12 V, 15 V, and 20 V gate drivers. |
| UVLO Thresholds | Configurable at 4 V, 8 V, 12 V, or 15 V - prevents erratic switching during brown-out conditions while matching common gate driver supply rails. |
| SelVCD™ Levels | 8 discrete sourcing/sinking current settings - eliminates need for external gate resistors and enables dynamic turn-on/turn-off speed tuning. |
| Operating Temp | –40 °C to +125 °C - qualified per AEC-Q100 Grade 1 for automotive-grade operation in engine bay and traction inverter applications. |
Pinout & Package
Narrow-body 16-pin SOIC (SOIC-16 NB) package with 1.27 mm pitch and creepage ≥8.3 mm. Pin 1 marked by dot; pins 12 and 13 are NC (no connection). Isolation barrier separates input-side (pins 1–8, 16) from output-side (pins 9–11, 14–15).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for driver A | CMOS-compatible, Schmitt-triggered input controlling VOA directly; deglitched for noise immunity. |
| VIB | Non-inverting logic input for driver B | Independent control path for VOB; enables true dual-driver operation without shared PWM logic. |
| EN | Active-high enable signal | Asserting EN = high enables both outputs; deasserting forces VOA/VOB low unconditionally - used for system-level fault shutdown. |
| DT | Dead time programming input | Resistor-to-GND sets dead time (10–110 kΩ → ~10–120 ns); connecting to VDDI disables dead time for universal dual-driver mode. |
| SPD+ | Sourcing current programming input | Resistor-to-GND selects one of eight turn-on current levels; enables gate drive strength optimization without discrete resistors. |
| SPD− | Sinking current programming input | Resistor-to-GND selects one of eight turn-off current levels; works in tandem with SPD+ to balance rise/fall times and minimize Miller-induced shoot-through. |
| VDDA / GNDA | Power and ground for driver A | Independent supply domain for high-side or low-side output stage; supports split-rail configurations and separate UVLO monitoring. |
| VDDB / GNDB | Power and ground for driver B | Electrically isolated from VDDA/GNDA; allows asymmetric gate drive voltages (e.g., +15 V/–5 V) for enhanced SiC FET control. |
| VDDI / GNDI | Logic input power and ground | Galvanically isolated input supply domain; decouples digital control from noisy power domains and enables floating controller interfaces. |
| VOA / VOB | Driver A and B outputs | Current-source outputs with integrated Miller clamp; sink/source up to 4 A peak (per SelVCD™ setting); no external gate resistors required. |
Key Features
| Feature | Design Value |
|---|---|
| Selectable Variable Current Drive (SelVCD™) | Eight discrete sourcing/sinking current levels set via SPD+/SPD− resistors - replaces gate resistors and enables adaptive switching speed tuning for EMI/efficiency trade-offs. |
| Integrated Miller Clamp | Automatically engages when VOA/VOB falls below VMCTA/B (~2.5 V typical) - suppresses Miller-induced false turn-on during high dV/dt commutation without external components. |
| Programmable Dead Time | Resistor-controlled DT pin sets dead time from ~10 ns to ~120 ns - prevents shoot-through in half-bridge configurations while retaining flexibility for universal dual-driver use. |
| AEC-Q100 Qualified | Grade 1 (–40 °C to +125 °C) qualification with automotive-specific manufacturing flow - ensures low defectivity and long-term reliability in traction and charging systems. |
| No Unknown Output States | Defined VOA/VOB logic-low state during UVLO, power loss, or EN deassertion - eliminates risk of unintended power switch conduction during fault or startup conditions. |
| High CMTI & Low Skew | 200 kV/μs common-mode transient immunity and <5 ns channel-to-channel skew - maintains timing integrity in fast-switching SiC/GaN inverters with >50 V/ns transients. |
Applications
| Onboard Charger (OBC) | Industrial Motor Drive |
|---|---|
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV onboard chargers using SiC MOSFET half-bridges. IC Role / Device Role / Timing Role: Isolated dual gate driver providing independent, skew-controlled turn-on/turn-off of high-side and low-side SiC switches with programmable dead time. Use Value: Enables >100 kHz switching with minimal shoot-through risk and reduced EMI via SelVCD™-tuned edge rates - critical for meeting CISPR-25 Class 5 emissions limits. |
Use Scenario: Field-oriented control (FOC) of permanent magnet synchronous motors (PMSM) in HVAC and industrial automation inverters. IC Role / Device Role / Timing Role: Universal-configured gate driver delivering precise, isolated timing to IGBTs or SiC modules with synchronized enable/disable and Miller clamping. Use Value: Eliminates external gate resistors and Miller diodes while maintaining <5 ns skew - improves torque ripple performance and thermal margin under overload conditions. |
| Uninterruptible Power Supply (UPS) | DC-DC Converter for Server PSU |
|
Use Scenario: High-efficiency 3-phase inverter stage in online UPS systems with battery backup and grid synchronization. IC Role / Device Role / Timing Role: Dual isolated driver managing complementary switching in three half-bridge legs with coordinated EN-based system shutdown. Use Value: 6 kVRMS isolation and 1500 VRMS working voltage meet IEC 62368-1 safety requirements for double-insulated UPS designs without additional creepage/clearance measures. |
Use Scenario: 48 V–12 V or 48 V–5 V non-isolated buck converters in AI server power delivery networks (PDNs) using GaN FETs. IC Role / Device Role / Timing Role: High-speed gate driver with ultra-low propagation delay skew ensuring clean zero-voltage switching (ZVS) in multi-phase interleaved topologies. Use Value: 200 kV/μs CMTI prevents false triggering from adjacent high-current phases; SelVCD™ allows fine-tuning of GaN gate drive to minimize reverse conduction losses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239AD-IS3R | Same SOIC-16 NB package and Universal configuration, but uses DIS (disable) instead of EN (enable) logic; identical SelVCD™, CMTI, and isolation specs. | Requires active-high disable signal instead of enable; truth table behavior differs during fault handling - DIS asserts low-side priority in overlap protection. | Select Si8239AD-IS3R only if system architecture mandates disable-first safety sequencing rather than enable-gated operation. |
| UCC5870QDWJRQ1 | Texas Instruments part with 5.7 kVRMS isolation, 100 kV/μs CMTI, and integrated DESAT detection; requires external gate resistors and lacks SelVCD™ current-source architecture. | Includes built-in desaturation fault reporting and higher peak output current (10 A), but adds complexity with external components and lacks Miller clamp integration. | Choose UCC5870QDWJRQ1 when desat protection is mandatory and board space allows for gate resistors and filter components; SI82F39AEE-IS3R preferred for resistorless, Miller-clamped simplicity. |
Compared with Si8239AD-IS3R, SI82F39AEE-IS3R offers enable-driven control for safer default-off behavior; versus UCC5870QDWJRQ1, it eliminates gate resistors and integrates Miller clamping - reducing BOM count and layout sensitivity in high-density SiC/GaN designs.
Availability
SI82F39AEE-IS3R is available at Aetrix Electronics and suitable for onboard chargers, industrial motor drives, uninterruptible power supplies, and server DC-DC converters requiring stable component supply, automotive-grade reliability, and resistorless gate drive implementation.
Supply support for SI82F39AEE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for automotive, infrastructure, and industrial markets.
The Si82Fx family was designed specifically for high-reliability isolated gate driving in next-generation power electronics - emphasizing capacitor-based isolation, SelVCD™ current-source architecture, and AEC-Q100 qualification for SiC/GaN-based traction and charging systems.
FAQ
What is the isolation voltage rating of the SI82F39AEE-IS3R?
The SI82F39AEE-IS3R is rated for 6 kVRMS isolation for 1 minute per UL 1577, with 1500 VRMS working voltage and compliance to VDE 60747-17, CSA 62368-1, and GB4943.1 standards. This reinforced insulation rating enables its use in safety-critical applications such as automotive onboard chargers and industrial inverters where galvanic separation between control and power domains is mandatory.
Does the SI82F39AEE-IS3R require external gate resistors?
No, the SI82F39AEE-IS3R does not require external gate resistors due to its Selectable Variable Current Drive (SelVCD™) architecture. The device operates as a precision current source with eight programmable sourcing and sinking levels set via SPD+ and SPD− pins. This eliminates gate resistor placement, reduces component count, and enables dynamic switching speed tuning - a key advantage over traditional voltage-mode gate drivers like the UCC5870QDWJRQ1.
How is dead time configured on the SI82F39AEE-IS3R?
Dead time on the SI82F39AEE-IS3R is configured using an external resistor (RDT) connected between the DT pin and GNDI. Values from 10 kΩ to 110 kΩ yield typical dead times from ~10 ns to ~120 ns, calculated as tDT = 1.73 × RDT + 5.74 (ns). Connecting DT to VDDI disables dead time insertion entirely, allowing the SI82F39AEE-IS3R to operate in universal dual-driver mode without overlap protection.
What is the function of the Miller clamp in the SI82F39AEE-IS3R?
The Miller clamp in the SI82F39AEE-IS3R engages automatically when VOA or VOB falls below VMCTA/B (~2.5 V), temporarily boosting sinking current to SPD7− level to suppress Miller-induced false turn-on during high dV/dt transitions. It operates directly through the VOA/VOB pins - requiring no external diodes or resistors - and disengages only upon the next VOH-to-VOL transition, ensuring robust immunity against parasitic turn-on in SiC and GaN FETs.
Is the SI82F39AEE-IS3R qualified for automotive applications?
Yes, the SI82F39AEE-IS3R is AEC-Q100 Grade 1 qualified (–40 °C to +125 °C) and built using automotive-specific manufacturing flows. It supports automotive applications including traction inverters and onboard chargers, with safety certifications pending for UL 1577, CSA 62368-1 (2 MOPP), and VDE 60747-17 - confirming suitability for ASIL-B system integration where reinforced isolation and long-term reliability are required.
SI82F39AEE-IS3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82F39AEE-IS3R FAQ
1.How can I place an order for SI82F39AEE-IS3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82F39AEE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82F39AEE-IS3R reliable?
The price and inventory of SI82F39AEE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82F39AEE-IS3R is usually 5 days.
3.What payment methods are accepted for SI82F39AEE-IS3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82F39AEE-IS3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82F39AEE-IS3R?
SI82F39AEE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82F39AEE-IS3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82F39AEE-IS3R?
For technical support, including SI82F39AEE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82F39AEE-IS3R requirements.
6.How does Aetrix verify that SI82F39AEE-IS3R is sourced from the original manufacturer or authorized distributors?
All SI82F39AEE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82F39AEE-IS3R meets industry standards.
7.What is the process for return or replacement of SI82F39AEE-IS3R?
All SI82F39AEE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82F39AEE-IS3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82F39AEE-IS3R part is unused and in its original packaging.
Return procedure for SI82F39AEE-IS3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI82F39AEE-IS3R Tags
-
TLP152(TPL,E
Toshiba Semiconductor and Storage

-
HT0740LG-G
Microchip Technology

-
FOD8314TR2
onsemi

-
1EDI60N12AFXUMA1
Infineon Technologies

-
1EDB7275FXUMA1
Infineon Technologies

-
UCC5350MCDR
Texas Instruments

-
2EDB7259KXUMA1
Infineon Technologies

-
UCC5304DWVR
Texas Instruments

-
SI8261BBC-C-ISR
Skyworks Solutions Inc.

-
HT0440LG-G
Microchip Technology

-
HCPL-0302-500E
Broadcom Limited

-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
