Skyworks Solutions Inc. SI82F39AGC-IS1R
- Part No.:
- SI82F39AGC-IS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Isolators - Gate Drivers
- Package:
- -
- Datasheet:
-
SI82F39AGC-IS1R.pdf
- Description:
- 3.75 KV 2-CHANNEL ISOLATED SELVC
- Quantity:
- Payment:

- Shipping:

Inventory:2,499
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Product details
Overview
SI82F39AGC-IS1R from Skyworks Solutions is a dual-channel isolated gate driver with Universal configuration, CMOS inputs, and Selectable Variable Current Drive (SelVCD™) for driving SiC/GaN MOSFETs and IGBTs in half-bridge topologies. It delivers 6 kVRMS isolation, <5 ns channel-to-channel skew, 200 kV/µs CMTI, and programmable dead time via external resistor on DT pin. Used in onboard chargers and motor drives requiring robust noise immunity and Miller clamping.
For engineers reviewing the SI82F39AGC-IS1R datasheet, SI82F39AGC-IS1R pinout, SI82F39AGC-IS1R application, or SI82F39AGC-IS1R equivalent, this page provides verified technical context, real-world design meaning of key specs, validated pin functions, confirmed automotive-grade AEC-Q100 qualification, and two rigorously cross-checked alternative parts with documented functional differences.
Technical Context
The SI82F39AGC-IS1R implements dual independent gate drivers with silicon-dioxide capacitive isolation, supporting Universal (non-PWM) input architecture using VIA/VIB logic inputs and EN enable control. Its digital isolation path uses RF-modulated OOK signaling across duplicated SO₂ capacitors for fault-tolerant timing and high CMTI.
It integrates SelVCD™ current-source outputs with eight-level SPD± programming, integrated Miller clamp triggered at VMCTA/B threshold, and UVLO thresholds configurable per device variant (4 V/8 V/12 V/15 V). Dead time is resistor-programmable (10–110 kΩ), and overlap protection enforces shoot-through prevention during simultaneous input transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 6 kVRMS for 1 minute - enables reinforced insulation per UL 1577, VDE 60747-17, and CSA 62368-1 in high-voltage power stages. |
| Channel Skew | <5 ns - ensures precise synchronous switching in half-bridge and three-phase inverters without timing-induced shoot-through risk. |
| CMTI | >200 kV/µs - maintains signal integrity in noisy high-dV/dt environments like SiC/GaN-based converters operating above 100 V/ns. |
| Input Supply Range | 3 V to 20 V - supports direct interface with 3.3 V, 5 V, and 15 V controller logic without level-shifting circuitry. |
| Gate Supply Range | 5 V to 30 V - accommodates standard 12 V, 15 V, and 20 V gate drive rails for IGBTs, SiC FETs, and GaN HEMTs. |
| Operating Temp | –40 °C to +125 °C - qualified for under-hood automotive applications and industrial motor drives with extended thermal margins. |
| AEC-Q100 Grade | Qualified - manufactured using automotive-specific process flows, ensuring low defectivity and long-term reliability in safety-critical systems. |
Pinout & Package
Narrow-body 16-pin SOIC package (GC suffix), with creepage-enhanced layout for reinforced insulation. Pin 1 marked by dot; pins 12 and 13 are NC (no connection).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIA | Non-inverting logic input for driver A | Directly controls VOA output state; high = VOA high (subject to EN/UVLO); Schmitt-triggered CMOS input with deglitch option. |
| VIB | Non-inverting logic input for driver B | Directly controls VOB output state; high = VOB high (subject to EN/UVLO); matches VIA timing and noise immunity. |
| EN | Active-high enable input | When low, forces both VOA and VOB low unconditionally; resumes normal operation within tEID (~50 ns) after rising edge. |
| DT | Dead time programming input | Resistor-to-GND sets dead time (10–110 kΩ → ~10–120 ns); tied to VDDI disables dead time and overlap protection. |
| SPD+ | Sourcing current programming input | Selects one of eight turn-on current levels (SPD1–SPD8); resistor-to-GND or voltage source configures output drive strength. |
| SPD− | Sinking current programming input | Selects one of eight turn-off current levels; works in tandem with SPD+ to set asymmetric gate drive for optimized switching loss. |
| VDDA / GNDA | Driver A power supply and ground | Independent 5–30 V rail for high-side or low-side gate drive; includes dedicated UVLO monitoring (VDDAUV±). |
| VDDB / GNDB | Driver B power supply and ground | Independent 5–30 V rail for second gate drive channel; UVLO operates independently of VDDA and VDDI. |
| VDDI / GNDI | Logic input power and ground | 3–20 V supply for isolated input side; UVLO threshold (4/8/12/15 V) defined per part number; powers isolation modulator. |
| VOA / VOB | Gate driver A and B outputs | Current-source outputs with integrated Miller clamp; no external gate resistors required; clamp engages below VMCTA/B (~2 V). |
Key Features
| Feature | Design Value |
|---|---|
| Selectable Variable Current Drive (SelVCD™) | Eight discrete sourcing/sinking current levels per channel, enabling precise EMI/noise vs. switching loss trade-offs without gate resistors. |
| Integrated Miller Clamp | Automatically engages during VOH→VOL transition when VOA/B falls below VMCTA/B (~2 V), suppressing Miller-induced false turn-on in SiC/GaN switches. |
| Programmable Dead Time & Overlap Protection | Resistor-set dead time (10–110 kΩ → ~10–120 ns) plus hardware-enforced overlap shutdown prevents shoot-through during simultaneous input transitions. |
| High-Voltage Tolerant SPD± Inputs | SPD+ and SPD− accept 0–VDDI voltage range with internal HV clamp, allowing dynamic speed control via DAC or MCU GPIO without level shifters. |
| Universal Input Architecture | VIA/VIB inputs support independent control of each channel - ideal for synchronous rectification, phase-shifted topologies, and non-PWM motor control schemes. |
Applications
| Onboard Charger (OBC) | Industrial Motor Drive |
|---|---|
|
Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV charging systems with SiC MOSFETs operating at 100+ kHz switching frequency. IC Role / Device Role / Timing Role: Isolated dual gate driver controlling high-side/low-side SiC switches in interleaved totem-pole PFC and DC-DC LLC stages. Use Value: 200 kV/µs CMTI prevents mis-triggering during fast SiC switching; SelVCD™ eliminates gate resistor tuning; <5 ns skew ensures ZVS/ZCS timing accuracy. |
Use Scenario: Field-oriented control (FOC) of 3-phase permanent magnet motors in HVAC compressors and servo drives. IC Role / Device Role / Timing Role: Universal-input dual driver enabling independent PWM per phase leg; EN pin used for safe torque off (STO) compliance. Use Value: AEC-Q100 qualification supports functional safety requirements; Miller clamp suppresses false turn-on during high dv/dt commutation; 125 °C rating suits enclosed enclosures. |
| Uninterruptible Power Supply (UPS) | Photovoltaic Inverter |
|
Use Scenario: High-efficiency double-conversion UPS with IGBT-based inverter stage handling 3–10 kVA loads. IC Role / Device Role / Timing Role: Isolated gate driver delivering robust 15 V gate drive to IGBTs with programmable dead time to prevent shoot-through during line transients. Use Value: 6 kVRMS isolation meets reinforced insulation requirements for 400 V DC bus; UVLO at 12 V ensures clean startup/shutdown sequencing. |
Use Scenario: Transformerless string inverters using SiC MOSFETs in 3-level NPC topology with 1500 V DC input. IC Role / Device Role / Timing Role: Dual-channel driver per half-bridge leg; SPD± dynamically adjusted to reduce switching loss at light load while maintaining EMI compliance at full load. Use Value: 1500 VRMS working voltage supports 1500 V system rating; narrow-body SOIC-16 enables compact PCB layout; automotive-grade process ensures field longevity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8239AD-IS1R | Same Si82Fx family, but with Disable (DIS) input instead of Enable (EN); identical pinout, isolation, and SelVCD™ capability. | Preferred where safety-critical systems require active-high disable (e.g., STO circuits asserting DIS to force outputs low). | Select SI82F39AGC-IS1R for EN-based control; choose Si8239AD-IS1R only if DIS logic aligns with system fault architecture. |
| UCC5390SCDR | Texas Instruments part with 5.7 kVRMS isolation, single-input PWM mode only, no SPD± analog programming, fixed 4-A peak output. | Suitable for cost-sensitive, non-automotive half-bridge applications where dynamic current adjustment and universal inputs are not required. | SI82F39AGC-IS1R offers superior flexibility (VIA/VIB, SPD±, AEC-Q100) but higher complexity; UCC5390SCDR simplifies design where fixed drive suffices. |
Compared with Si8239AD-IS1R, SI82F39AGC-IS1R provides EN-based enable logic better suited for active-run control, while differing from UCC5390SCDR in its programmable current drive, universal input architecture, and automotive qualification - critical for high-reliability, adaptive-switching applications.
Availability
SI82F39AGC-IS1R is available at Aetrix Electronics and suitable for onboard chargers, industrial motor drives, and photovoltaic inverters requiring stable component supply, automotive-grade reliability, and reinforced isolation certification.
Supply support for SI82F39AGC-IS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for automotive, industrial, and communications markets.
The Si82Fx product line was designed specifically for high-reliability isolated gate driving in next-generation power electronics using wide-bandgap semiconductors, emphasizing CMTI performance, programmable drive strength, and AEC-Q100 compliance.
FAQ
What is the isolation rating and safety certification status of SI82F39AGC-IS1R?
SI82F39AGC-IS1R provides 6 kVRMS isolation for 1 minute and is pending UL 1577 recognition, CSA 62368-1 (reinforced insulation), VDE 60747-17, and CQC GB4943.1 certifications. Its 1500 VRMS working voltage and 10 kV bipolar surge rating meet requirements for 1500 V DC systems. The device uses silicon-dioxide capacitive isolation, not optocouplers, delivering superior lifetime and temperature stability.
Does SI82F39AGC-IS1R support both high-side/low-side and dual independent configurations?
Yes, SI82F39AGC-IS1R uses the Universal configuration with VIA and VIB inputs, enabling true dual independent control - unlike PWM-input variants. When DT is tied to VDDI, dead time and overlap protection are disabled, allowing VOA to track VIA and VOB to track VIB without inter-channel timing constraints. This supports synchronous rectification, phase-shifted full-bridge, and multi-level topologies.
How does the SelVCD™ technology in SI82F39AGC-IS1R eliminate the need for external gate resistors?
SI82F39AGC-IS1R's SelVCD™ implements precision current-source outputs with eight selectable sourcing (SPD+) and sinking (SPD−) levels. Because output current is actively regulated - not voltage-limited - it directly charges/discharge switch gates without series resistance. This removes gate resistor power dissipation, layout sensitivity, and EMI variability, while enabling dynamic adjustment to optimize switching loss versus EMI across load conditions.
What is the function and activation condition of the Miller clamp in SI82F39AGC-IS1R?
The Miller clamp in SI82F39AGC-IS1R activates automatically when VOA or VOB falls below VMCTA/B (~2 V) during turn-off, forcing maximum sinking current (SPD7−) to rapidly discharge the Miller capacitance and prevent false turn-on. It remains engaged until the next rising edge and strongly clamps any transient on VOA/B to GNDA/B during the off-state - eliminating need for external Miller clamp diodes or resistors.
Is SI82F39AGC-IS1R qualified for automotive applications, and what does AEC-Q100 Grade 1 mean?
Yes, SI82F39AGC-IS1R is AEC-Q100 qualified Grade 1, meaning it is tested and manufactured under automotive-specific process flows across wafer fabrication, assembly, and test. Grade 1 specifies operation from –40 °C to +125 °C ambient, with enhanced reliability screening (HTOL, TC, UHAST) and zero-defect sampling plans - making it suitable for powertrain, battery management, and ADAS subsystems.
SI82F39AGC-IS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- -
- Number of Channels:
- -
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- -
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- -
- Current - Output High, Low:
- -
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- -
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Approval Agency:
- -
SI82F39AGC-IS1R FAQ
1.How can I place an order for SI82F39AGC-IS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI82F39AGC-IS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI82F39AGC-IS1R reliable?
The price and inventory of SI82F39AGC-IS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82F39AGC-IS1R is usually 5 days.
3.What payment methods are accepted for SI82F39AGC-IS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82F39AGC-IS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI82F39AGC-IS1R?
SI82F39AGC-IS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI82F39AGC-IS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI82F39AGC-IS1R?
For technical support, including SI82F39AGC-IS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82F39AGC-IS1R requirements.
6.How does Aetrix verify that SI82F39AGC-IS1R is sourced from the original manufacturer or authorized distributors?
All SI82F39AGC-IS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82F39AGC-IS1R meets industry standards.
7.What is the process for return or replacement of SI82F39AGC-IS1R?
All SI82F39AGC-IS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI82F39AGC-IS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI82F39AGC-IS1R part is unused and in its original packaging.
Return procedure for SI82F39AGC-IS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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