Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Isolators > Isolators - Gate Drivers

Skyworks Solutions Inc. SI82F39EEE-IS3R

Name: SI82F39EEE-IS3R
Brand: Skyworks Solutions Inc.
SKU: SI82F39EEE-IS3R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI82F39EEE-IS3R

Manufacturer:: Skyworks Solutions Inc.

Category:: Isolators - Gate Drivers

Package:: -

Datasheet:: SI82F39EEE-IS3R.pdf

Description:: 6 KV 2-CHANNEL ISOLATED SELVCD G

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,570

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI82F39EEE-IS3R from Skyworks Solutions is a dual-channel isolated gate driver with Universal configuration and EN input, designed for high-side/low-side half-bridge control in SiC/GaN-based power converters. It delivers 6 kVRMS isolation, <5 ns channel-to-channel skew, 200 kV/μs CMTI, and Selectable Variable Current Drive (SelVCD™) across eight sourcing/sinking levels - enabling direct gate drive of wide-bandgap FETs in onboard chargers and motor drives.

For engineers reviewing the SI82F39EEE-IS3R datasheet, SI82F39EEE-IS3R pinout, SI82F39EEE-IS3R application, or SI82F39EEE-IS3R equivalent, key selection criteria include its 3–20 V logic supply range, programmable dead time via external resistor, integrated Miller clamp, automotive-grade AEC-Q100 qualification, and narrow-body 16-pin SOIC package with reinforced insulation per UL 1577, VDE 60747-17, and IEC 62368-1.

Technical Context

The SI82F39EEE-IS3R implements dual CMOS-isolated channels using differential RF-modulated capacitive coupling across silicon dioxide barriers, delivering functional and safety isolation up to 6 kVRMS. Its Universal pinout supports independent non-inverting inputs (VIA/VIB) and active-high enable (EN), with dead time programmability via DT pin and analog speed control via SPD+/SPD− pins.

It features independent UVLO monitoring on VDDI (4 V/8 V/12 V/15 V options), GNDA/VDDB-referenced outputs operating as precision current sources, and built-in Miller clamp activation triggered at VMCTA/B threshold during VO→VOL transitions - all without external gate resistors.

Key Specifications

Parameter	Value and Actual Design Meaning
Isolation Voltage	6 kVRMS for 1 minute - meets reinforced insulation requirements per UL, VDE, and IEC standards.
Channel Skew	<5 ns - ensures precise timing alignment between high-side and low-side gate drive signals.
CMTI	>200 kV/μs - prevents false triggering in noisy high-dV/dt environments like SiC inverters.
Logic Supply Range	3 V to 20 V - compatible with 3.3 V, 5 V, and 15 V controller interfaces without level shifting.
Gate Drive Supply	5 V to 30 V - supports direct connection to bootstrap or isolated DC-DC supplies for SiC/GaN FETs.
SelVCD™ Levels	8 discrete sourcing/sinking current settings - eliminates need for external gate resistors and enables dynamic turn-on/turn-off optimization.
Operating Temp	–40 °C to +125 °C - qualified for under-hood automotive and industrial ambient conditions.
AEC-Q100 Grade	Qualified - manufactured with automotive-specific process flows for low defectivity and long-term reliability.

Pinout & Package

Narrow-body 16-pin SOIC (SOIC-16NB) package with creepage/clearance optimized for reinforced insulation. Pin 1 marked by dot; Pins 12 and 13 are NC (no connection).

Pin/Terminal	Circuit Role	Design Meaning
VIA	Non-inverting logic input A	Drives VOA high when asserted; CMOS-compatible with deglitch filter option.
VIB	Non-inverting logic input B	Drives VOB high when asserted; independent of VIA for dual-driver operation.
EN	Active-high enable	Unconditionally forces VOA/VOB low when deasserted; enables fast system-level shutdown.
DT	Dead time programming	Resistor-to-GND sets dead time (10–110 kΩ → ~10–190 ns); connect to VDDI to disable.
SPD+	Sourcing current control	Resistor-to-GND selects one of eight turn-on current levels; enables Miller clamp integration.
SPD−	Sinking current control	Resistor-to-GND selects one of eight turn-off current levels; activates Miller clamp at VMCT threshold.
VDDA / GNDA	High-side gate driver supply	Provides 5–30 V power and ground reference for VOA output stage.
VDDB / GNDB	Low-side gate driver supply	Provides independent 5–30 V power and ground reference for VOB output stage.
VDDI / GNDI	Logic input supply	3–20 V supply with UVLO monitoring; powers isolation barrier and input logic.
VOA / VOB	Isolated gate drive outputs	Current-source outputs with integrated Miller clamp; no external gate resistors required.

Key Features

Feature	Design Value
Selectable Variable Current Drive (SelVCD™)	Eight discrete sourcing/sinking current levels set via SPD+/SPD− resistors - replaces gate resistors and enables adaptive switching loss optimization.
Integrated Miller Clamp	Automatically engages when VOA/VOB falls below VMCTA/B during turn-off - suppresses Miller-induced false turn-on in SiC/GaN FETs without external components.
Programmable Dead Time	External resistor on DT pin sets dead time (10–110 kΩ → ~10–190 ns); disabled by connecting DT to VDDI for universal dual-driver mode.
High CMTI & Low Skew	200 kV/μs common-mode transient immunity and <5 ns channel-to-channel skew - ensures robust timing integrity in high-frequency, high-power topologies.
Automotive-Grade Qualification	AEC-Q100 qualified with manufacturing flow optimized for zero-defect automotive applications - suitable for OBC, traction inverter, and EPS systems.
Reinforced Safety Isolation	6 kVRMS isolation rating with UL 1577, VDE 60747-17, and IEC 62368-1 certification - enables single-package isolation in safety-critical 400 V/800 V systems.

Applications

Motor Drives	Onboard Chargers (OBC)
Use Scenario: Three-phase inverter driving PMSM/IM motors in EV traction or industrial servo systems. IC Role / Device Role / Timing Role: Dual isolated gate driver providing synchronized, skew-controlled high-side/low-side drive with programmable dead time to prevent shoot-through. Use Value: Enables >100 kHz switching with SiC FETs while maintaining <5 ns timing margin and eliminating external gate resistors and Miller clamps.	Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV onboard chargers with 400 V/800 V battery interfaces. IC Role / Device Role / Timing Role: Isolated gate driver for interleaved totem-pole PFC and CLLC resonant DC/DC stages requiring reinforced insulation and high CMTI. Use Value: 6 kVRMS isolation and 200 kV/μs CMTI ensure reliable operation across primary-secondary boundaries in compact, high-density OBC designs.
Power Inverters	Uninterruptible Power Supplies (UPS)
Use Scenario: Grid-tied solar inverters and energy storage systems using SiC MOSFETs in three-level NPC or T-type topologies. IC Role / Device Role / Timing Role: Universal-configured isolated driver supporting independent high-side/low-side control with configurable UVLO thresholds for varying bus voltages. Use Value: SelVCD™ allows fine-tuning of switching losses across variable load conditions; AEC-Q100 grade supports extended field lifetime in outdoor installations.	Use Scenario: Online double-conversion UPS systems requiring fast, reliable transfer between utility and battery backup with minimal output disturbance. IC Role / Device Role / Timing Role: Gate driver for IGBT/SiC half-bridges in inverter stage, where precise dead time control prevents cross-conduction during mode transitions. Use Value: <5 ns skew and programmable dead time ensure clean, jitter-free PWM edge alignment - critical for maintaining THD <3% in 50/60 Hz output waveforms.

Motor Drives

Onboard Chargers (OBC)

Use Scenario: Three-phase inverter driving PMSM/IM motors in EV traction or industrial servo systems.

IC Role / Device Role / Timing Role: Dual isolated gate driver providing synchronized, skew-controlled high-side/low-side drive with programmable dead time to prevent shoot-through.

Use Value: Enables >100 kHz switching with SiC FETs while maintaining <5 ns timing margin and eliminating external gate resistors and Miller clamps.

Use Scenario: Bidirectional AC/DC and DC/DC conversion in EV onboard chargers with 400 V/800 V battery interfaces.

IC Role / Device Role / Timing Role: Isolated gate driver for interleaved totem-pole PFC and CLLC resonant DC/DC stages requiring reinforced insulation and high CMTI.

Use Value: 6 kVRMS isolation and 200 kV/μs CMTI ensure reliable operation across primary-secondary boundaries in compact, high-density OBC designs.

Power Inverters

Uninterruptible Power Supplies (UPS)

Use Scenario: Grid-tied solar inverters and energy storage systems using SiC MOSFETs in three-level NPC or T-type topologies.

IC Role / Device Role / Timing Role: Universal-configured isolated driver supporting independent high-side/low-side control with configurable UVLO thresholds for varying bus voltages.

Use Value: SelVCD™ allows fine-tuning of switching losses across variable load conditions; AEC-Q100 grade supports extended field lifetime in outdoor installations.

Use Scenario: Online double-conversion UPS systems requiring fast, reliable transfer between utility and battery backup with minimal output disturbance.

IC Role / Device Role / Timing Role: Gate driver for IGBT/SiC half-bridges in inverter stage, where precise dead time control prevents cross-conduction during mode transitions.

Use Value: <5 ns skew and programmable dead time ensure clean, jitter-free PWM edge alignment - critical for maintaining THD <3% in 50/60 Hz output waveforms.

Equivalent & Alternatives

The following parts are listed as comparable options for similar isolated dual-channel gate driver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si8239EE-IS3R	Same Si82Fx family, but with DIS (disable) instead of EN (enable) input logic; identical pinout and specs otherwise.	Preferred where system-level fault handling requires active-high disable assertion rather than enable activation.	Select SI82F39EEE-IS3R for EN-based control architecture; Si8239EE-IS3R for DIS-based architectures - not pin-compatible due to differing input logic polarity.
UCC5390SCDR	Texas Instruments part with 5.7 kVRMS isolation, 150 kV/μs CMTI, and fixed 4-A peak drive - lacks SelVCD™, Miller clamp, and programmable dead time.	Better suited for cost-sensitive, non-automotive applications where adjustable drive strength and integrated protection are not required.	Choose SI82F39EEE-IS3R when SelVCD™, Miller clamp, AEC-Q100, or programmable dead time are mandatory; UCC5390SCDR where simplicity and TI ecosystem support are prioritized.

Compared with Si8239EE-IS3R, SI82F39EEE-IS3R provides EN-based system control with identical isolation and timing performance but different fault-handling semantics; versus UCC5390SCDR, it adds eight-level current drive, integrated Miller clamp, and automotive qualification - at the cost of higher design complexity and component count for SPD± resistors.

Availability

SI82F39EEE-IS3R is available at Aetrix Electronics and suitable for motor drives, onboard chargers, power inverters, and uninterruptible power supplies requiring stable component supply, automotive-grade reliability, and reinforced safety isolation.

Supply support for SI82F39EEE-IS3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.

The Si82Fx family was designed specifically for isolated gate driving of wide-bandgap power devices in high-reliability, high-efficiency power conversion systems - emphasizing timing precision, noise immunity, and integration of protection features like Miller clamp and programmable dead time.

FAQ

What is the isolation voltage rating of the SI82F39EEE-IS3R?

The SI82F39EEE-IS3R has a safety-rated isolation voltage of 6 kVRMS for 1 minute, certified to UL 1577, VDE 60747-17, and IEC 62368-1 standards. This reinforced insulation rating supports use in 400 V and 800 V automotive and industrial systems where galvanic separation between control and power domains is mandatory. The isolation barrier uses dual silicon dioxide capacitors for fault tolerance and low skew.

Does the SI82F39EEE-IS3R support both high-side/low-side and dual independent configurations?

Yes, the SI82F39EEE-IS3R operates in Universal configuration, supporting both modes. When the DT pin is connected to GND via a resistor, it functions as a high-side/low-side driver with programmable dead time. When DT is tied to VDDI, dead time and overlap protection are disabled, allowing independent control of VOA and VOB via VIA and VIB - effectively operating as two isolated single-channel drivers.

How does the SelVCD™ feature eliminate the need for external gate resistors in the SI82F39EEE-IS3R?

SelVCD™ makes the SI82F39EEE-IS3R's VOA and VOB outputs behave as precision current sources across eight user-selectable levels (via SPD+/SPD− resistors). Because output current is actively regulated - not voltage-limited - gate charging/discharging is controlled directly by current magnitude and duration, removing reliance on RC time constants. This also enables the integrated Miller clamp to function through the same output pin without interference from series resistance.

What is the role of the Miller clamp in the SI82F39EEE-IS3R, and when does it activate?

The Miller clamp in the SI82F39EEE-IS3R activates automatically when VOA or VOB falls below the VMCTA/B threshold (~2–3 V typical) during turn-off transitions. It maximizes sinking current (to SPD7− level) to rapidly discharge the Miller capacitance of SiC/GaN FETs and prevent false turn-on. The clamp remains engaged until the next rising edge, and requires no external components - but only functions correctly if no gate resistor is placed between VOA/VOB and the FET gate.

Is the SI82F39EEE-IS3R qualified for automotive applications?

Yes, the SI82F39EEE-IS3R is AEC-Q100 qualified and designated as an automotive-grade part. It is manufactured using automotive-specific process flows across wafer fabrication, assembly, and test - ensuring low defectivity, robustness against thermal cycling and vibration, and long-term reliability in under-hood environments. Its 125 °C max operating temperature and reinforced isolation support use in EV onboard chargers, traction inverters, and DC-DC converters.

SI82F39EEE-IS3R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Technology:: -

Number of Channels:: -

Voltage - Isolation:: -

Common Mode Transient Immunity (Min):: -

Propagation Delay tpLH / tpHL (Max):: -

Pulse Width Distortion (Max):: -

Rise / Fall Time (Typ):: -

Current - Output High, Low:: -

Current - Peak Output:: -

Voltage - Forward (Vf) (Typ):: -

Current - DC Forward (If) (Max):: -

Voltage - Output Supply:: -

Grade:: -

Qualification:: -

Operating Temperature:: -

Mounting Type:: -

Supplier Device Package:: -

Approval Agency:: -

SI82F39EEE-IS3R FAQ

1.How can I place an order for SI82F39EEE-IS3R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI82F39EEE-IS3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI82F39EEE-IS3R reliable?

The price and inventory of SI82F39EEE-IS3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI82F39EEE-IS3R is usually 5 days.

3.What payment methods are accepted for SI82F39EEE-IS3R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI82F39EEE-IS3R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI82F39EEE-IS3R?

SI82F39EEE-IS3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI82F39EEE-IS3R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI82F39EEE-IS3R?

For technical support, including SI82F39EEE-IS3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI82F39EEE-IS3R requirements.

6.How does Aetrix verify that SI82F39EEE-IS3R is sourced from the original manufacturer or authorized distributors?

All SI82F39EEE-IS3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI82F39EEE-IS3R meets industry standards.

7.What is the process for return or replacement of SI82F39EEE-IS3R?

All SI82F39EEE-IS3R units undergo pre-shipment inspection (PSI). If there is an issue with SI82F39EEE-IS3R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI82F39EEE-IS3R part is unused and in its original packaging.

Return procedure for SI82F39EEE-IS3R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…