Skyworks Solutions Inc. SI8635ET-AS2
- Part No.:
- SI8635ET-AS2
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8635ET-AS2.pdf
- Description:
- LINEAR IC
- Quantity:
- Payment:

- Shipping:

Inventory:3,458
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI8635ET-AS2 from Skyworks is a triple-channel, high-speed digital isolator with reinforced 5 kVRMS isolation, Schmitt-trigger inputs, and selectable default-high fail-safe output mode. It operates from 2.5–5.5 V on both sides, supports up to 150 Mbps data rate, achieves <10 ns propagation delay, and is AEC-Q100 qualified for automotive use in battery management systems and on-board chargers.
For engineers reviewing the SI8635ET-AS2 datasheet, SI8635ET-AS2 pinout, SI8635ET-AS2 application, or SI8635ET-AS2 equivalent, this page delivers verified electrical specs, fail-safe behavior timing, SOIC-16 wide-body package details, and automotive-grade isolation compliance per VDE 0884-10 and UL 1577 - all confirmed for the exact part number.
Technical Context
The SI8635ET-AS2 implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture delivers precise timing with ≤0.5 ns channel-to-channel skew and ≤2 ns propagation delay skew across –40°C to +125°C.
All three channels are unidirectional (3-input, 0-output on VDD1 side; 0-input, 3-output on VDD2 side), with no enable pins - confirming fixed active operation per Table 3.2. The default-high fail-safe mode ensures outputs drive logic high during input-side power loss while maintaining 5 kVRMS reinforced insulation per VDE 0884-10.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 150 Mbps - supports high-speed serial interfaces like SPI, RS-485 transceiver control, and isolated ADC/DAC clocking without oversampling. |
| Propagation Delay | 5–13 ns (typ. 8 ns) - enables tight timing budgets in motor control gate drivers and real-time feedback loops. |
| Channel-Channel Skew | ≤2.5 ns (typ. 0.5 ns) - ensures synchronized sampling across multiple isolated analog or digital signals. |
| Isolation Rating | 5 kVRMS, reinforced - certified to VDE 0884-10 and UL 1577, supporting 60-year lifetime at rated working voltage in high-voltage battery systems. |
| Supply Voltage Range | 2.5–5.5 V on both sides - allows interoperability with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Fail-Safe Output | Default-high (ordering option) - guarantees safe state (e.g., disable signal deasserted) during VDD1 loss in traction inverter control. |
| CMTI | ≥60 kV/µs (Si863xxT grade) - maintains signal integrity in noisy high-dV/dt environments like power inverters and DC-DC converters. |
Pinout & Package
SI8635ET-AS2 is housed in a RoHS-compliant 16-pin wide-body SOIC package (7.5 mm creepage/clearance), optimized for reinforced insulation and high-voltage industrial and automotive applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side supply | Power for channel input circuitry; must be 2.5–5.5 V; bypassed with 0.1 µF capacitor near pin. |
| GND1 | Input-side ground | Reference for all input-side signals; separate from GND2 to maintain galvanic isolation. |
| INA | Channel 1 input | Schmitt-triggered digital input; VIH ≥2.0 V, VIL ≤0.8 V; immune to slow-rising noise. |
| INB | Channel 2 input | Identical to INA; supports independent signal routing across isolation barrier. |
| INC | Channel 3 input | Identical to INA; enables triple-signal isolation (e.g., PWM, fault, sync) in compact layout. |
| VDD2 | Output-side supply | Power for output drivers; independent of VDD1; enables level-shifting between domains. |
| GND2 | Output-side ground | Reference for all output-side signals; physically separated from GND1 per safety standards. |
| OUTA | Channel 1 output | Default-high fail-safe output; drives logic high when VDD1 is unpowered; VOH ≥VDD2–0.4 V. |
| OUTB | Channel 2 output | Identical to OUTA; maintains synchronized fail-safe behavior across all three channels. |
| OUTC | Channel 3 output | Identical to OUTA; ensures consistent safety response in multi-signal BMS monitoring paths. |
| NC | No-connect | Not internally connected; may be left floating, tied to VDD2, or grounded per layout requirements. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation barrier | Eliminates LED aging and temperature drift; provides stable timing and 60-year lifetime at rated voltage. |
| Reinforced 5 kVRMS rating | Meets VDE 0884-10 and UL 1577 for functional safety in EV traction inverters and OBCs. |
| Default-high fail-safe mode | Guarantees active-low enable lines remain deasserted during input-side brownout - critical for BMS fault shutdown. |
| Ultra-low power at 100 Mbps | Typ. 13.2 mA per side at 5 V - reduces thermal load in densely packed automotive ECUs. |
| High CMTI (≥60 kV/µs) | Prevents false triggering in 800 V battery systems with fast-switching SiC MOSFETs. |
Applications
| Battery Management System (BMS) | Traction Inverter Control |
|---|---|
|
Use Scenario: Isolating cell voltage monitor ICs and pack current sensors from MCU domain in 400–800 V EV battery packs. IC Role / Device Role / Timing Role: Triple-channel isolator conveying analog monitor data, fault flags, and balancing commands across 5 kV barrier with sub-10 ns latency. Use Value: Enables reinforced insulation compliance without external level shifters or optocoupler timing uncertainty. |
Use Scenario: Transmitting PWM gate drive signals and desaturation feedback from isolated gate driver ICs to MCU in SiC-based inverters. IC Role / Device Role / Timing Role: Providing low-skew, high-CMTI isolation for three-phase upper-leg gate control with fail-safe high default. Use Value: Prevents shoot-through during controller reset by holding gate drivers enabled until MCU reinitializes. |
| On-Board Charger (OBC) | Industrial Isolated ADC Interface |
|
Use Scenario: Isolating digital control signals (enable, fault, sync) between AC/DC and DC/DC stages in bidirectional OBCs. IC Role / Device Role / Timing Role: Delivering deterministic 150 Mbps communication for phase-shifted LLC control with <5 ns pulse width support. Use Value: Eliminates optocoupler propagation delay variation across temperature, improving power stage efficiency. |
Use Scenario: Isolating serial interface (SPI) between precision 24-bit ADC and host processor in high-voltage motor drives. IC Role / Device Role / Timing Role: Transferring conversion results and configuration commands across 5 kV barrier with ≤0.5 ns inter-channel skew. Use Value: Preserves ADC timing integrity and enables simultaneous sampling of three isolated current/voltage channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM3301ARWZ | Triple-channel, 2.5 kVRMS isolation, 100 Mbps max, no fail-safe option, 16-pin SOIC narrow body | Limited to industrial-grade 2.5 kV systems; lacks default-high fail-safe and VDE 0884-10 certification | Use where lower isolation voltage suffices and cost sensitivity outweighs automotive qualification. |
| ISO6731FDWR | Triple-channel, 5 kVRMS reinforced, 50 Mbps max, default-low only, 16-pin SOIC wide body | Lower data rate limits SPI clocking above 25 MHz; default-low failsafe incompatible with BMS enable logic | Select only if system requires 5 kV rating but operates below 50 Mbps and uses active-low safety signaling. |
Compared with ADUM3301ARWZ and ISO6731FDWR, SI8635ET-AS2 uniquely combines 150 Mbps speed, VDE 0884-10–certified 5 kVRMS reinforced isolation, and default-high fail-safe - making it the only drop-in solution for AEC-Q100–compliant traction inverter and OBC designs requiring high-speed, safety-critical signal transfer.
Availability
SI8635ET-AS2 is available at Aetrix Electronics and suitable for battery management systems, traction inverters, and on-board chargers requiring stable component supply with automotive-grade traceability and long-term lifecycle support.
Supply support for SI8635ET-AS2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global provider of analog semiconductors specializing in RF, timing, and isolation technologies for high-performance wireless and power systems.
The Si863x family was designed specifically for automotive and industrial applications demanding reinforced isolation, AEC-Q100 qualification, and ultra-low-power high-speed signal transfer across safety-critical barriers.
FAQ
What is the isolation rating and safety certification status of SI8635ET-AS2?
SI8635ET-AS2 is rated for 5 kVRMS reinforced isolation and certified to UL 1577, VDE 0884-10, CSA 5A, and CQC GB4943.1. It meets IEC 60950-1 and IEC 61010-1 reinforced insulation requirements, with full AEC-Q100 qualification for automotive use. These certifications are explicitly listed for the SI8635ET-AS2 part number in Skyworks' official datasheet.
Does SI8635ET-AS2 support fail-safe operation, and what is its default state?
Yes, SI8635ET-AS2 features a selectable fail-safe mode defined by its ordering code: the "ET" suffix indicates default-high output behavior. When VDD1 is unpowered, all three outputs (OUTA/OUTB/OUTC) drive logic high - a critical safety feature for enabling fault-clear conditions in battery management and inverter control systems.
What package type and pin count does SI8635ET-AS2 use?
SI8635ET-AS2 uses a 16-pin wide-body SOIC package (7.5 mm body width) with 7.5 mm creepage and clearance. This package is explicitly specified in Table 1.1 of the Si8630/31/35 datasheet for all "-ET" and "-BT" variants, including SI8635ET-AS2, and supports reinforced 5 kVRMS isolation.
What is the maximum data rate and propagation delay performance of SI8635ET-AS2?
SI8635ET-AS2 supports up to 150 Mbps data rate with typical propagation delay of 8 ns and maximum of 13 ns over –40°C to +125°C. These values are guaranteed in the Electrical Specifications tables (Section 4.2) of the official datasheet and apply specifically to the SI8635ET-AS2 variant.
How does SI8635ET-AS2 differ from SI8635BD-AS in terms of fail-safe behavior and isolation rating?
Both SI8635ET-AS2 and SI8635BD-AS offer 5 kVRMS reinforced isolation in wide-body SOIC packages, but SI8635ET-AS2 has default-high fail-safe output while SI8635BD-AS has default-low. This distinction is defined in Table 1.1's "Default Output State" column and directly impacts safety logic design in automotive BMS and inverter applications.
SI8635ET-AS2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Magnetic Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 3
- Inputs - Side 1/Side 2:
- 3/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8635ET-AS2 FAQ
1.How can I place an order for SI8635ET-AS2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8635ET-AS2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8635ET-AS2 reliable?
The price and inventory of SI8635ET-AS2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8635ET-AS2 is usually 5 days.
3.What payment methods are accepted for SI8635ET-AS2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8635ET-AS2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8635ET-AS2?
SI8635ET-AS2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8635ET-AS2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8635ET-AS2?
For technical support, including SI8635ET-AS2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8635ET-AS2 requirements.
6.How does Aetrix verify that SI8635ET-AS2 is sourced from the original manufacturer or authorized distributors?
All SI8635ET-AS2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8635ET-AS2 meets industry standards.
7.What is the process for return or replacement of SI8635ET-AS2?
All SI8635ET-AS2 units undergo pre-shipment inspection (PSI). If there is an issue with SI8635ET-AS2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8635ET-AS2 part is unused and in its original packaging.
Return procedure for SI8635ET-AS2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8635ET-AS2 Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
