Skyworks Solutions Inc. SI8640BD-ASR
- Part No.:
- SI8640BD-ASR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8640BD-ASR.pdf
- Description:
- LOW-POWER, QUAD-CHANNEL DIGITAL
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8640BD-ASR from Skyworks is a quad-channel, unidirectional digital isolator with 4 input channels on VDD1 side and 0 on VDD2 side, rated for 5.0 kVRMS reinforced isolation in wide-body SOIC-16 package. It supports DC–150 Mbps data rates, achieves <10 ns propagation delay (typ. 8 ns), and operates across –40 to +125 °C with fail-safe default-low output state - used in isolated gate drivers for traction inverters and battery management systems.
For engineers reviewing the SI8640BD-ASR datasheet, SI8640BD-ASR pinout, SI8640BD-ASR application, or SI8640BD-ASR equivalent, key selection criteria include its 5.0 kVRMS reinforced insulation (VDE 0884-10 certified), ultra-low power consumption (1.6 mA/channel @ 1 Mbps, 5 V), Schmitt-trigger inputs for noise immunity, and tri-state outputs controlled by single EN pin - all critical for automotive-grade high-voltage system isolation.
Technical Context
The SI8640BD-ASR implements RF-based on/off keying across a silicon-die isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture delivers precise timing with ≤0.5 ns channel-channel skew and ≤2 ns propagation delay skew, supporting deterministic signal integrity in safety-critical motor control loops.
All four channels are unidirectional (A→B), with inputs on Side A (VDD1) and outputs on Side B (VDD2). The single enable input (EN) resides on Side B and places all four outputs into high-impedance when low - enabling shared-bus arbitration and power sequencing in isolated communication interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5.0 kVRMS reinforced (VDE 0884-10, UL 1577, CSA 5A, CQC GB4943.1) - enables direct interface with 800 V DC bus systems without additional creepage reinforcement. |
| Data Rate | DC to 150 Mbps - supports high-speed SPI, CAN FD, and PWM feedback in real-time motor control and battery monitoring. |
| Propagation Delay | 5.0–13.0 ns (typ. 8.0 ns) - ensures sub-10 ns latency for fast-response protection circuits in inverters and chargers. |
| Power Consumption | 1.6 mA per channel @ 1 Mbps / 5 V - reduces thermal load in densely packed automotive ECUs and extends system-level efficiency. |
| Common-Mode Transient Immunity | 60 kV/µs (min) - maintains signal integrity during rapid voltage transients in high-di/dt power stages (e.g., SiC/GaN switching). |
| Operating Temperature | –40 to +125 °C - qualified per AEC-Q100 Grade 1, suitable for under-hood and battery-pack environments. |
| Fail-Safe Default | Low-output state during VDD1 loss - prevents unintended gate turn-on in isolated IGBT/SiC driver applications. |
Pinout & Package
SI8640BD-ASR uses a RoHS-compliant wide-body SOIC-16 package (WB SOIC-16, 10.3 mm × 7.5 mm, 8 mm creepage) with reinforced insulation. Pin functions are validated per Skyworks Si864x datasheet Section 5 (Pin Descriptions) and Figure 5.1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side supply | 2.5–5.5 V power for input logic and RF transmitter; bypassed with 0.1 µF capacitor near pin. |
| GND1 | Input-side ground | Reference for all Side A signals; must be separated from GND2 by isolation barrier. |
| INA1–INA4 | Input channels | Unidirectional digital inputs with Schmitt-trigger thresholds (VT+ = 1.67 V typ, VT– = 1.23 V typ) for >400 mV hysteresis. |
| VDD2 | Output-side supply | 2.5–5.5 V power for RF receiver and output drivers; independent of VDD1 for true galvanic isolation. |
| GND2 | Output-side ground | Reference for all Side B outputs; forms isolated domain with VDD2. |
| EN | Enable control | Active-high enable on Side B; drives all four outputs to high-impedance when low - enables bus sharing and safe power-down. |
| OUTB1–OUTB4 | Output channels | CMOS-compatible outputs (VOH ≥ VDD2–0.4 V, VOL ≤ 0.4 V @ 4 mA); 50 Ω nominal impedance for controlled-impedance routing. |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced VDE 0884-10 certification | Validated 10 kV surge capability and 60-year lifetime at rated working voltage - eliminates need for external transient protection in EV powertrain designs. |
| Tri-state output control via single EN pin | Enables dynamic bus arbitration and hot-swap capability in multi-isolator systems without requiring per-channel enable logic. |
| Schmitt-trigger inputs with 440 mV hysteresis | Rejects >100 MHz noise and EFT bursts in noisy motor drive environments - no external filtering required. |
| Ultra-low propagation delay skew | ≤0.5 ns channel-to-channel skew ensures synchronized sampling of multi-phase current/voltage feedback in motor controllers. |
| AEC-Q100 Grade 1 qualification | Full automotive process flow with PPAP, IMDS/CAMDS support - meets OEM requirements for battery electric vehicle (BEV) and hybrid systems. |
Applications
| On-Board Charger (OBC) | Battery Management System (BMS) |
|---|---|
Use Scenario: Isolating 3.3 V microcontroller SPI commands from 800 V DC-link sensing circuitry in bidirectional OBCs. IC Role / Device Role / Timing Role: Quad-channel unidirectional isolator transmitting gate drive enable, fault status, and ADC readback across primary-secondary barrier. Use Value: 5.0 kVRMS reinforced rating eliminates need for external creepage extenders; <10 ns delay preserves tight PWM timing margins in ZVS/ZCS topologies. |
Use Scenario: Isolating cell voltage monitor ICs (e.g., LTC6813) from MCU in high-cell-count BEV battery packs. IC Role / Device Role / Timing Role: Transmitting precision analog front-end data and balancing commands across isolation barrier with fail-safe low-default state. Use Value: Default-low behavior prevents false cell-balancing activation during power-up; AEC-Q100 qualification ensures reliability over 15-year pack life. |
| Traction Inverter | Industrial Motor Drive |
Use Scenario: Providing isolated gate drive signals to SiC half-bridge modules in 400–800 V traction inverters. IC Role / Device Role / Timing Role: Delivering matched-delay PWM signals to upper/lower gate drivers while rejecting common-mode dv/dt noise up to 100 kV/µs. Use Value: 60 kV/µs CMTI and ≤0.5 ns skew maintain shoot-through immunity; wide-temp operation supports liquid-cooled inverter housings. |
Use Scenario: Isolating encoder feedback and current sense signals in servo drives operating in factory automation environments. IC Role / Device Role / Timing Role: Transmitting quadrature encoder pulses and isolated shunt amplifier outputs to motion controller with minimal jitter. Use Value: 350 ps peak eye diagram jitter preserves position resolution; 150 Mbps capability supports high-resolution multi-turn encoders. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM2400ARWZ | 4.0 kVRMS basic isolation (UL/IEC 60747-5-2), 25 Mbps max data rate, no fail-safe mode, 25 ns propagation delay. | Limited to industrial SMPS and PLC I/O where 150 Mbps and reinforced insulation are not required. | Select only if cost sensitivity outweighs performance and safety requirements; not suitable for automotive or 800 V systems. |
| ISO7741FDWR | 5.0 kVRMS reinforced (VDE 0884-10), 100 Mbps max, 11 ns propagation delay, default-high only, no EN pin. | Acceptable for non-automotive BMS and solar inverters but lacks tri-state control and AEC-Q100 qualification. | Choose when tri-state control is unnecessary and AEC-Q100 is not mandated; verify default-high compatibility with system logic. |
Compared with ADUM2400ARWZ and ISO7741FDWR, SI8640BD-ASR delivers 6× higher data rate, 2.5× lower propagation delay, integrated EN control, and full automotive qualification - making it the only option meeting ISO 26262 ASIL-B requirements for traction inverter gate drive isolation.
Availability
SI8640BD-ASR is available at Aetrix Electronics and suitable for automotive battery management systems, on-board chargers, traction inverters, and industrial motor drives requiring stable component supply across extended temperature and high-reliability lifecycles.
Supply support for SI8640BD-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si864x family was designed specifically for high-reliability, high-speed galvanic isolation in automotive electrification and industrial power conversion - emphasizing reinforced safety, ultra-low latency, and AEC-Q100 compliance from wafer to shipment.
FAQ
What is the isolation rating and safety certification of SI8640BD-ASR?
SI8640BD-ASR is rated for 5.0 kVRMS reinforced isolation and certified to VDE 0884-10, UL 1577, CSA Component Notice 5A, IEC 62368-1, and CQC GB4943.1. These certifications validate its suitability for functional safety applications in automotive traction inverters and industrial equipment operating up to 800 V DC bus voltages.
Does SI8640BD-ASR support fail-safe operation during power loss?
Yes, SI8640BD-ASR features a selectable fail-safe mode with default-low output state when VDD1 is unpowered but VDD2 remains active. This behavior prevents unintended activation of downstream gate drivers or actuators during brown-out conditions - a critical requirement in battery management and motor control systems.
What is the function of the EN pin on SI8640BD-ASR?
The EN pin on SI8640BD-ASR is an active-high enable input located on the output side (VDD2 domain). When pulled low, it places all four output pins (OUTB1–OUTB4) into high-impedance state - enabling dynamic bus sharing, safe power sequencing, and reduced standby current in multi-isolator configurations.
How does SI8640BD-ASR achieve ultra-low power consumption?
SI8640BD-ASR achieves ultra-low power via RF-based on/off keying instead of pulse-width modulation or capacitive coupling. At 1 Mbps and 5 V, it draws only 1.6 mA per channel - significantly lower than optocoupler or older capacitive isolators - reducing thermal stress and extending battery runtime in portable and automotive systems.
Is SI8640BD-ASR qualified for automotive applications?
Yes, SI8640BD-ASR is AEC-Q100 Grade 1 qualified and manufactured using full automotive process flows, including AIAG-compliant PPAP documentation, IMDS/CAMDS material declarations, and zero-defect methodology - making it suitable for battery electric vehicles, hybrid powertrains, and charging infrastructure.
SI8640BD-ASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si864x
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8640BD-ASR FAQ
1.How can I place an order for SI8640BD-ASR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8640BD-ASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8640BD-ASR reliable?
The price and inventory of SI8640BD-ASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8640BD-ASR is usually 5 days.
3.What payment methods are accepted for SI8640BD-ASR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8640BD-ASR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8640BD-ASR?
SI8640BD-ASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8640BD-ASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8640BD-ASR?
For technical support, including SI8640BD-ASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8640BD-ASR requirements.
6.How does Aetrix verify that SI8640BD-ASR is sourced from the original manufacturer or authorized distributors?
All SI8640BD-ASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8640BD-ASR meets industry standards.
7.What is the process for return or replacement of SI8640BD-ASR?
All SI8640BD-ASR units undergo pre-shipment inspection (PSI). If there is an issue with SI8640BD-ASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8640BD-ASR part is unused and in its original packaging.
Return procedure for SI8640BD-ASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8640BD-ASR Tags
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ISO1212DBQR
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ISO6721BDR
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SI8710AC-B-ISR
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ISO7720FDR
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SI8710CC-B-ISR
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ISO6741FQDWRQ1
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ISO7762FDBQR
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ISO7741DWR
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ISO7741FDWR
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