Skyworks Solutions Inc. SI8640ED-ASR
- Part No.:
- SI8640ED-ASR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8640ED-ASR.pdf
- Description:
- AUTOMOTIVE LOW-POWER, QUAD-CHANN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8640ED-ASR from Skyworks is a quad-channel, unidirectional digital isolator with 4 input channels on VDD1 side and 0 on VDD2 side, rated for 5.0 kVRMS reinforced isolation in wide-body SOIC-16 package. It supports up to 150 Mbps data rate, achieves <10 ns propagation delay, and features selectable high-default fail-safe output mode. It is used in isolated gate drivers and battery management systems where high-voltage domain separation and noise immunity are critical.
For engineers reviewing the SI8640ED-ASR datasheet, SI8640ED-ASR pinout, SI8640ED-ASR application, or SI8640ED-ASR equivalent, key selection criteria include its 5.0 kVRMS reinforced insulation rating (VDE 0884-10), automotive-grade AEC-Q100 qualification, tri-state enable control, Schmitt-trigger inputs, and ultra-low power consumption at 100 Mbps (3.5 mA per channel @ 2.5 V).
Technical Context
The SI8640ED-ASR implements RF-based on/off keying across a silicon dioxide isolation barrier, eliminating startup initialization and enabling robust operation without optical degradation. Its architecture delivers precise timing with ≤2.5 ns channel-to-channel skew and ≤4.5 ns pulse width distortion across –40°C to +125°C.
All four channels reside on the input side (VDD1), with outputs on VDD2 side driven by a single enable input (EN) referenced to VDD2. The device uses internal undervoltage lockout (UVLO) on both sides and supports fail-safe default-high output during input-side power loss - a factory-configured ordering option confirmed for this part number.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - supports high-speed serial interfaces like SPI, RS-485 transceiver control, and isolated ADC/DAC clocking. |
| Isolation rating | 5.0 kVRMS reinforced - certified to VDE 0884-10 and UL 1577, enabling use in medical (IEC 60601-1) and industrial (IEC 62368-1) safety-critical systems. |
| Propagation delay | 5.0–13 ns - ensures tight timing alignment in motor control PWM feedback loops and real-time power converter monitoring. |
| Supply voltage | 2.5–5.5 V per side - allows interoperability with 3.3 V microcontrollers and 5 V analog front-ends without level-shifting. |
| Power @ 100 Mbps | 3.5 mA/channel @ 2.5 V - enables low-power battery-backed BMS monitoring with minimal thermal impact in compact enclosures. |
| Fail-safe default | High - guarantees active logic-high output during VDD1 loss, critical for safe shutdown signaling in traction inverters. |
| CMTI | ≥60 kV/µs - maintains signal integrity in high-dV/dt environments such as SiC/GaN inverter switching nodes. |
Pinout & Package
SI8640ED-ASR is housed in a RoHS-compliant wide-body SOIC-16 package (WB SOIC-16, -AS suffix), with 8 mm creepage and reinforced insulation suitable for 5.0 kVRMS working voltage. Pinout follows standard Si864x layout for 4-input/0-output configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side supply | Power for input logic and RF transmitter; must be bypassed with 0.1 µF capacitor near pin. |
| GND1 | Input-side ground | Reference return for VDD1 and all input signals (A1–A4); requires low-inductance connection. |
| A1–A4 | Input channels | CMOS/Schmitt-trigger inputs accepting 2.0–5.5 V logic; no external pull-up/down required. |
| VDD2 | Output-side supply | Power for RF receiver and output drivers; independent of VDD1 for true galvanic isolation. |
| GND2 | Output-side ground | Reference return for VDD2 and all output signals (B1–B4); physically separated from GND1. |
| B1–B4 | Output channels | Push-pull CMOS outputs with ~50 Ω impedance; support 4 mA sink/source at 0.4 V/4.8 V levels. |
| EN | Enable control | Active-high input on VDD2 side; drives all B1–B4 into high-impedance when low - enables shared-bus arbitration. |
| NC | No-connect | Pins 1, 9, 16 are unconnected; may be left floating, tied to VDD2, or grounded per layout best practices. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation barrier | Silicon dioxide dielectric enables 60-year lifetime at rated voltage and eliminates LED aging concerns of optocouplers. |
| Selectably high-default output | Factory-set fail-safe behavior ensures B1–B4 remain logic-high during VDD1 loss - critical for fault-signaling in EV battery packs. |
| Tri-state enable with EN | Single-pin control disables all four outputs simultaneously into high-Z, simplifying bus sharing and reducing contention risk. |
| Ultra-low power at 2.5 V | 1.5 mA/channel @ 1 Mbps enables always-on monitoring in energy-constrained automotive subsystems. |
| Automotive-grade qualification | AEC-Q100 Grade 1 (–40°C to +125°C) with AIAG PPAP support ensures reliability in on-board chargers and traction inverters. |
Applications
| Isolated Gate Driver Interface | Battery Management System (BMS) |
|---|---|
Use Scenario: Isolating PWM control signals between MCU and high-side IGBT/SiC gate drivers in motor inverters. IC Role / Device Role / Timing Role: Quad-channel unidirectional isolator transmitting four independent gate-enable signals with sub-10 ns timing precision. Use Value: Enables safe 5.0 kVRMS separation between low-voltage control logic and 800 V DC bus, while maintaining <2.5 ns channel skew for synchronized switching. | Use Scenario: Monitoring cell voltages and temperatures across 96-cell EV battery stacks using isolated ADC interfaces. IC Role / Device Role / Timing Role: Providing isolated communication paths from high-voltage battery modules to central BMS controller. Use Value: Fail-safe high-default output ensures open-wire fault detection remains active even during partial power loss in module electronics. |
| Industrial PLC I/O Module | Medical Isolated Data Acquisition |
Use Scenario: Digitally isolating 24 V DC field inputs (limit switches, sensors) from 3.3 V PLC backplane logic. IC Role / Device Role / Timing Role: Converting industrial-level inputs to clean CMOS logic with Schmitt-trigger noise immunity. Use Value: 60 kV/µs CMTI prevents false triggering in electrically noisy factory environments with variable-frequency drives. | Use Scenario: Isolating ECG/EEG analog front-end digitization circuits from USB-connected host processors in diagnostic equipment. IC Role / Device Role / Timing Role: Transmitting digitized patient data across reinforced insulation barrier compliant with IEC 60601-1. Use Value: VDE 0884-10 certification and 5.0 kVRMS rating satisfy patient-isolation requirements without external creepage extenders. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM140D0BRWZ | Quad-channel, 5.0 kVRMS, 150 Mbps, but only 3.0 V to 5.5 V supply range; no 2.5 V operation. | Lacks AEC-Q100 qualification and failsafe-high ordering option; not approved for automotive BMS. | Prefer SI8640ED-ASR when 2.5 V compatibility, automotive qualification, or guaranteed high-default state is required. |
| ISO6741FDWR | Quad-channel, 5.0 kVRMS, 50 Mbps max data rate; higher power consumption (7.5 mA/channel @ 100 Mbps). | Qualified to IEC 60747-17 but not VDE 0884-10; limited to industrial, not medical or automotive. | Choose SI8640ED-ASR for high-speed (150 Mbps), low-power, and safety-certified designs requiring reinforced insulation. |
Compared with ADUM140D0BRWZ and ISO6741FDWR, SI8640ED-ASR uniquely combines 150 Mbps speed, 2.5 V operation, AEC-Q100 Grade 1, VDE 0884-10 certification, and factory-configurable fail-safe high output - making it optimal for next-generation EV and medical isolation architectures.
Availability
SI8640ED-ASR is available at Aetrix Electronics and suitable for battery management systems, traction inverters, and medical data acquisition requiring stable component supply across automotive and industrial lifecycles.
Supply support for SI8640ED-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si864x family was designed specifically for high-reliability, high-speed digital isolation in automotive, industrial, and medical systems demanding long-term stability, low power, and certified reinforced insulation.
FAQ
What is the isolation rating and safety certification status of SI8640ED-ASR?
SI8640ED-ASR is rated for 5.0 kVRMS reinforced isolation and certified to UL 1577, CSA Component Notice 5A, VDE 0884-10 (reinforced), IEC 62368-1, and IEC 60601-1. These certifications validate its use in safety-critical applications including EV battery systems and medical diagnostics equipment where patient or operator protection is mandated.
Does SI8640ED-ASR support operation at 2.5 V on both sides?
Yes, SI8640ED-ASR operates across 2.5–5.5 V on both VDD1 and VDD2 supplies. At 2.5 V, it draws only 1.5 mA per channel at 1 Mbps and 3.5 mA per channel at 100 Mbps - enabling direct interface with ultra-low-voltage microcontrollers and extending battery life in portable medical or automotive subsystems.
How does the fail-safe default-high feature work in SI8640ED-ASR?
In SI8640ED-ASR, the default output state is factory-configured as high. When VDD1 is unpowered but VDD2 remains active, outputs B1–B4 drive logic-high - a behavior confirmed in Table 3.1 and Ordering Guide for "ED" suffix parts. This ensures fail-safe signaling in applications like BMS fault lines or emergency stop circuits.
What is the function of the EN pin on SI8640ED-ASR?
The EN pin on SI8640ED-ASR is an active-high enable input referenced to VDD2. When EN = low, all four outputs (B1–B4) enter high-impedance state - allowing multiple isolators to share a common bus or enabling dynamic power gating. Timing specs show enable-to-valid delay ≤11 ns and enable-to-tri-state ≤12 ns.
Is SI8640ED-ASR qualified for automotive applications?
Yes, SI8640ED-ASR carries the "-A" suffix indicating automotive-grade qualification. It is AEC-Q100 Grade 1 qualified (–40°C to +125°C), manufactured using automotive-specific process flows, and supported with AIAG-compliant PPAP documentation - making it suitable for on-board chargers, battery management systems, and traction inverters.
SI8640ED-ASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si864x
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 4/0
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8640ED-ASR FAQ
1.How can I place an order for SI8640ED-ASR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8640ED-ASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8640ED-ASR reliable?
The price and inventory of SI8640ED-ASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8640ED-ASR is usually 5 days.
3.What payment methods are accepted for SI8640ED-ASR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8640ED-ASR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8640ED-ASR?
SI8640ED-ASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8640ED-ASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8640ED-ASR?
For technical support, including SI8640ED-ASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8640ED-ASR requirements.
6.How does Aetrix verify that SI8640ED-ASR is sourced from the original manufacturer or authorized distributors?
All SI8640ED-ASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8640ED-ASR meets industry standards.
7.What is the process for return or replacement of SI8640ED-ASR?
All SI8640ED-ASR units undergo pre-shipment inspection (PSI). If there is an issue with SI8640ED-ASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8640ED-ASR part is unused and in its original packaging.
Return procedure for SI8640ED-ASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8640ED-ASR Tags
-
ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

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ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

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ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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