Skyworks Solutions Inc. SI8641EB-AU
- Part No.:
- SI8641EB-AU
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI8641EB-AU.pdf
- Description:
- AUTOMOTIVE 2.5 KV 3 FORWARD & 1
- Quantity:
- Payment:

- Shipping:

Inventory:2,249
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI8641EB-AU from Skyworks is a quad-channel digital isolator with 3 input channels on VDD1 side and 1 output channel on VDD2 side, rated for 2.5 kVRMS isolation, 150 Mbps data rate, and –40 to 125 °C operation. It features Schmitt-trigger inputs, tri-state outputs with independent enable control (EN1/EN2), selectable high-default fail-safe mode, and ultra-low power consumption-1.4 mA per channel at 1 Mbps (5 V), enabling use in isolated motor control gate drivers and battery management system signal interfaces.
For engineers reviewing the SI8641EB-AU datasheet, SI8641EB-AU pinout, SI8641EB-AU application, or SI8641EB-AU equivalent, key selection criteria include channel asymmetry (3:1 input/output split), reinforced insulation certification (VDE 0884-10 basic), QSOP-16 package footprint, and fail-safe high default state-critical for safety-critical power stage enable signaling and isolated ADC/DAC control paths.
Technical Context
The SI8641EB-AU implements RF-based on/off keying across a silicon-die isolation barrier, eliminating startup initialization and providing stable timing across temperature. Its dual enable inputs (EN1 on VDD1 side for A4; EN2 on VDD2 side for B1–B3) support independent tri-state control of input and output sides, enabling dynamic channel gating in real-time control loops.
Each channel integrates Schmitt-trigger inputs (VT+ = 1.67 V typ, VT– = 1.23 V typ) for >400 mV hysteresis and 50 Ω nominal output impedance (±40%), supporting controlled-impedance PCB routing. Propagation delay is 8 ns typ (5–13 ns max), with 0.4 ns channel-channel skew and 2 ns propagation delay skew-enabling precise timing in isolated PWM feedback paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | DC to 150 Mbps - supports high-speed isolated communication in servo drives and fast-loop motor controllers. |
| Isolation Rating | 2.5 kVRMS - certified to UL 1577, CSA 5A, and basic VDE 0884-10 for industrial safety compliance. |
| Propagation Delay | 8 ns typical (5–13 ns max) - enables sub-10 ns timing-critical feedback in isolated gate driver circuits. |
| Supply Voltage | 2.5–5.5 V on both sides - allows interoperability with 3.3 V microcontrollers and 5 V analog front-ends. |
| Fail-Safe Default | High - ensures active-high enable signals remain asserted during VDD1 loss in BMS or inverter systems. |
| Power @ 1 Mbps | 1.4 mA per channel (VDD=5 V) - reduces thermal load in densely packed isolated power supply control boards. |
| CMTI | 60 kV/µs typical - maintains signal integrity in high-dV/dt environments like IGBT/SiC half-bridges. |
Pinout & Package
SI8641EB-AU is housed in a RoHS-compliant QSOP-16 package (5.3 mm × 10.2 mm, 1.0 mm height), optimized for high-density PCB layouts with 0.635 mm pitch and creepage ≥5.5 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side power supply | Supplies logic and RF transmitter circuitry for channels A1–A4; requires 0.1 µF bypass capacitor. |
| GND1 | Input-side ground reference | Return path for VDD1; must be separated from GND2 by isolation barrier. |
| A1–A3 | Digital inputs (VDD1 side) | 3-channel input interface with Schmitt-trigger thresholds; drive isolated output B1–B3. |
| A4 | Input with EN1 control | Input channel enabled only when EN1 = high; otherwise high-impedance. |
| EN1 | Enable for A4 output | Active-high control on VDD1 side; pulls up internally to VDD1 if left floating. |
| VDD2 | Output-side power supply | Supplies RF receiver and output drivers for B1–B3; independent of VDD1. |
| GND2 | Output-side ground reference | Return path for VDD2; galvanically isolated from GND1. |
| B1–B3 | Digital outputs (VDD2 side) | 3-channel isolated outputs driven by A1–A3; default high during VDD1 loss. |
| EN2 | Enable for B1–B3 outputs | Active-high control on VDD2 side; disables all three outputs into high-Z when low. |
| NC | No-connect terminal | Not internally bonded; may be left floating, tied to VDD2, or grounded per layout needs. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric 3:1 channel configuration | Optimizes signal routing in bidirectional isolated interfaces where control signals dominate (e.g., MCU-to-gate-driver command + status feedback). |
| Selectable high-default fail-safe mode | Ensures safe deactivation of power stages during input-side brownout-critical for ISO 26262 ASIL-B compliant inverters. |
| Independent dual-enable architecture | EN1 (VDD1 side) and EN2 (VDD2 side) allow synchronized or decoupled channel gating-reducing EMI during startup/shutdown sequences. |
| RF-based isolation barrier | Eliminates LED aging and temperature drift issues of optocouplers; guarantees 60-year life at rated working voltage. |
| 50 Ω output impedance | Enables direct connection to 50 Ω transmission lines without external termination-simplifying layout in high-speed isolated SPI or PWM links. |
Applications
| Motor Control Systems | Isolated Power Supply Monitoring |
|---|---|
Use Scenario: Isolating PWM enable signals and fault feedback between MCU and 3-phase IGBT/SiC gate drivers in servo amplifiers. IC Role / Device Role / Timing Role: SI8641EB-AU transmits 3x gate enable commands (A1–A3 → B1–B3) and receives one fault flag (A4 ← EN2-controlled return path), with <10 ns propagation delay ensuring tight loop timing. Use Value: Fail-safe high default prevents unintended gate turn-on during MCU reset, while 60 kV/µs CMTI rejects noise from fast-switching power stages. | Use Scenario: Monitoring isolated DC bus voltage and current sense signals in flyback or LLC converters with secondary-side regulation. IC Role / Device Role / Timing Role: SI8641EB-AU carries 3 analog-to-digital converter outputs (isolated via external ADC) and one enable signal for synchronous rectifier control. Use Value: 150 Mbps capability supports oversampled ADC data streaming; 2.5 kVRMS rating meets IEC 62368-1 reinforced insulation requirements for Class II power supplies. |
| Battery Management Systems | Industrial PLC I/O Modules |
Use Scenario: Interfacing cell monitoring ICs (e.g., LTC6813) to host controller across isolation barrier in EV traction battery packs. IC Role / Device Role / Timing Role: SI8641EB-AU routes 3x cell voltage readouts and one pack fault alert (A4), with EN2 used to disable outputs during hot-swap events. Use Value: High-default fail-safe ensures contactor remains closed during transient VDD1 dropout; AEC-Q100 qualification validates automotive-grade reliability. | Use Scenario: Isolating digital inputs from field sensors (24 V DC) and outputs to actuators in modular PLC backplanes. IC Role / Device Role / Timing Role: SI8641EB-AU provides 3-channel input sensing (dry contact, NAMUR) and 1-channel output control (relay driver enable), with Schmitt-trigger inputs rejecting line noise. Use Value: 1.23–1.67 V input hysteresis suppresses bounce in mechanical switch interfaces; QSOP-16 footprint fits compact DIN-rail mount modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM1401ARWZ | 4-channel symmetrical (2/2), 100 Mbps max, 2.5 kVRMS, SOIC-16WB, no selectable fail-safe default | Lacks asymmetric channel count and programmable fail-safe; requires external pull-ups for high-default behavior | Choose when symmetric 2:2 isolation suffices and board space permits wider SOIC-16WB package. |
| ISO6741QDWR | 4-channel symmetrical (2/2), 50 Mbps max, 5 kVRMS, SOIC-16NB, fails low by default | Lower speed and fixed low-default mode limit use in high-bandwidth or safety-critical high-enable systems | Prefer for cost-sensitive industrial I/O where 50 Mbps is adequate and low-default logic is acceptable. |
Compared with ADUM1401ARWZ and ISO6741QDWR, SI8641EB-AU uniquely delivers 3:1 channel asymmetry, 150 Mbps speed, and factory-configured high-default fail-safe in QSOP-16-making it optimal for space-constrained, high-reliability motor control and BMS designs requiring deterministic power-loss behavior.
Availability
SI8641EB-AU is available at Aetrix Electronics and suitable for motor control systems, battery management units, isolated power supply monitors, and industrial PLC I/O modules requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability.
Supply support for SI8641EB-AU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si864x family was engineered for high-reliability industrial and automotive isolation-delivering RF-based digital isolation with guaranteed 60-year life, AEC-Q100 qualification, and VDE/UL safety certifications to replace aging optocouplers in mission-critical power systems.
FAQ
What is the default output state of SI8641EB-AU during input-side power loss?
The SI8641EB-AU is configured with a high-default fail-safe mode. When VDD1 is unpowered but VDD2 remains active, outputs B1–B3 maintain a logic high state-ensuring safety-critical enable signals (e.g., to gate drivers) stay asserted until deliberate shutdown. This behavior is factory-set and cannot be changed in-circuit.
Does SI8641EB-AU require external components for stable operation?
Yes, SI8641EB-AU requires a 0.1 µF ceramic bypass capacitor between VDD1 and GND1, and another between VDD2 and GND2, placed within 2 mm of the respective pins. No pull-up/down resistors are needed-the device integrates internal 2 µA pull-ups on inputs/outputs for its high-default configuration.
Can SI8641EB-AU be used in automotive applications?
Yes, SI8641EB-AU is an automotive-grade part (denoted by "-AU" suffix), qualified to AEC-Q100 Grade 1 (–40 to 125 °C), supported with AIAG-compliant PPAP documentation, and listed in IMDS/CAMDS. It is deployed in on-board chargers, battery management systems, and traction inverters per Skyworks' automotive manufacturing flow.
How does the dual-enable feature (EN1 and EN2) function in SI8641EB-AU?
In SI8641EB-AU, EN1 (on VDD1 side) controls output A4's driver, while EN2 (on VDD2 side) controls outputs B1–B3. When EN1 = low, A4 enters high-impedance; when EN2 = low, B1–B3 enter high-impedance. Both pins are internally pulled up, allowing floating use-but external tie-off is recommended in noisy environments.
What safety certifications apply to SI8641EB-AU?
SI8641EB-AU holds UL 1577 (5000 VRMS/1 min), CSA Component Acceptance Notice 5A, and basic VDE 0884-10 certification. It meets IEC 62368-1 and IEC 60950-1 reinforced insulation requirements and is rated for 2.5 kVRMS working voltage per regulatory test standards.
SI8641EB-AU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si864x
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 4
- Inputs - Side 1/Side 2:
- 3/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI8641EB-AU FAQ
1.How can I place an order for SI8641EB-AU through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8641EB-AU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8641EB-AU reliable?
The price and inventory of SI8641EB-AU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8641EB-AU is usually 5 days.
3.What payment methods are accepted for SI8641EB-AU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8641EB-AU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8641EB-AU?
SI8641EB-AU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8641EB-AU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8641EB-AU?
For technical support, including SI8641EB-AU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8641EB-AU requirements.
6.How does Aetrix verify that SI8641EB-AU is sourced from the original manufacturer or authorized distributors?
All SI8641EB-AU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8641EB-AU meets industry standards.
7.What is the process for return or replacement of SI8641EB-AU?
All SI8641EB-AU units undergo pre-shipment inspection (PSI). If there is an issue with SI8641EB-AU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8641EB-AU part is unused and in its original packaging.
Return procedure for SI8641EB-AU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8641EB-AU Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
