Skyworks Solutions Inc. SI8652EB-B-IUR
- Part No.:
- SI8652EB-B-IUR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI8652EB-B-IUR.pdf
- Description:
- DGTL ISO 2500VRMS 5CH GP 16QSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8652EB-B-IUR from Skyworks is a five-channel digital isolator with 3 input channels on VDD1 side and 2 output channels on VDD2 side, supporting up to 150 Mbps data rate, <10 ns propagation delay, and 2.5 kVRMS isolation. It features Schmitt-trigger inputs, tri-state outputs with enable control, and selectable high-default fail-safe mode-used in isolated motor control, battery management systems, and industrial PLCs.
For engineers reviewing the SI8652EB-B-IUR datasheet, SI8652EB-B-IUR pinout, SI8652EB-B-IUR application, or SI8652EB-B-IUR equivalent, this page delivers verified electrical specs, QSOP-16 package details, fail-safe behavior under power loss, and real-world timing performance including 0.5 ns channel-channel skew and 50 kV/µs CMTI.
Technical Context
The SI8652EB-B-IUR implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its dual-enable architecture (EN1 for A4/A5, EN2 for B1/B2/B3) supports independent channel-group control and high-impedance output states during disable.
It operates across 2.5–5.5 V supply ranges on both sides, maintains stable timing over –40 to +125 °C, and integrates undervoltage lockout (UVLO) with 70 mV hysteresis per rail. The device achieves 5 ns minimum pulse width and 350 ps peak eye jitter at 150 Mbps, meeting reinforced insulation requirements per IEC 60950-1 and IEC 62368-1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 5 total: 3 inputs on VDD1 side, 2 outputs on VDD2 side - enables asymmetric signal routing across isolation barrier. |
| Max Data Rate | 150 Mbps - supports high-speed serial interfaces like SPI, RS-485 transceiver control, and isolated ADC/DAC clocking. |
| Propagation Delay | 5–13 ns - ensures sub-10 ns typical latency critical for real-time motor gate drive synchronization. |
| Isolation Rating | 2.5 kVRMS - certified to UL 1577, CSA 5A, VDE 0884-10, and CQC GB4943.1 for industrial safety compliance. |
| Supply Voltage | 2.5–5.5 V per side - allows direct interfacing with 3.3 V microcontrollers and 5 V analog subsystems without level shifters. |
| CMTI | ≥35 kV/µs - rejects fast common-mode transients in noisy motor drives and inverters without data corruption. |
| Fail-Safe Default | High - outputs remain logic high during VDD1 loss while VDD2 remains powered, preventing unintended system shutdown. |
Pinout & Package
SI8652EB-B-IUR is housed in a RoHS-compliant QSOP-16 narrow-body package (5.3 mm × 10.2 mm), rated for –40 to +125 °C operation and compatible with standard JEDEC reflow profiles (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side power supply | Supplies 2.5–5.5 V to input-side logic and channel transmitter; bypass capacitor required. |
| GND1 | Input-side ground reference | Return path for VDD1; must be separated from GND2 by creepage/clearance per safety standards. |
| A1–A3 | Input signals (VDD1 side) | Three digital inputs with Schmitt-trigger thresholds (VT+ = 1.67 V typ, VT– = 1.23 V typ) for noise immunity. |
| EN1 | Enable for A4/A5 outputs | Active-high control: drives A4/A5 into high-impedance when low; internally pulled up to VDD2 (2 µA). |
| VDD2 | Output-side power supply | Supplies 2.5–5.5 V to output-side logic and receiver; independent of VDD1 for true galvanic isolation. |
| GND2 | Output-side ground reference | Return path for VDD2; forms isolation barrier with GND1; defines secondary-side reference plane. |
| B1–B3 | Output signals (VDD2 side) | Three isolated outputs with 50 Ω nominal impedance; VOH ≥ VDD2–0.4 V, VOL ≤ 0.4 V at 4 mA. |
| EN2 | Enable for B1–B3 outputs | Active-high control: disables B1–B3 into high-impedance when low; internally pulled up to VDD2 (2 µA). |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates LED aging and temperature drift; enables >60-year life at rated working voltage with no startup delay. |
| Selectably high-fail-safe output | Outputs default to logic high during VDD1 loss - prevents latch-up in downstream drivers or gate controllers. |
| Tri-state outputs with dual enable | EN1 and EN2 independently disable A4/A5 and B1/B3 groups, enabling time-multiplexed bus sharing or safe power sequencing. |
| Precision timing performance | 0.5 ns channel-channel skew and 2 ns propagation delay skew ensure deterministic timing across all five channels. |
| Ultra-low power at 100 Mbps | 11.7–15.2 mA total supply current (VDD1 + VDD2) at 100 Mbps - reduces thermal load in dense industrial modules. |
Applications
| Motor Control Systems | Isolated Power Supply Monitoring |
|---|---|
Use Scenario: Gate driver isolation in three-phase inverter stages for HVAC compressors and servo drives. IC Role / Device Role / Timing Role: Isolates PWM signals from MCU to IGBT/SiC gate drivers while maintaining <10 ns propagation delay and tight channel skew. Use Value: Enables precise dead-time control and prevents shoot-through faults due to timing mismatch across isolated channels. |
Use Scenario: Monitoring primary-side voltage/current feedback in isolated DC-DC converters for telecom and server PSUs. IC Role / Device Role / Timing Role: Transfers analog-to-digital converter status bits and fault flags across isolation barrier with fail-safe high default. Use Value: Ensures fault reporting remains active during primary-side brownout, triggering safe shutdown before secondary overload. |
| Battery Management Systems | Industrial PLC I/O Modules |
Use Scenario: Cell voltage monitoring and pack-level communication isolation in EV battery packs. IC Role / Device Role / Timing Role: Isolates UART or SPI lines between battery monitor ICs and host controller, supporting 150 Mbps for fast cell balancing updates. Use Value: Maintains data integrity amid high dv/dt transients from contactor switching, validated at ≥50 kV/µs CMTI. |
Use Scenario: Digital input/output signal isolation in modular PLC backplanes handling 24 V DC field wiring. IC Role / Device Role / Timing Role: Provides five independent isolation paths for discrete sensor inputs and actuator outputs in compact QSOP-16 footprint. Use Value: Reduces PCB area vs. discrete optocouplers while delivering guaranteed 2.5 kVRMS isolation and AEC-Q100-compatible reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8652BB-B-IUR | Same QSOP-16 package and 3/2 channel split, but default output state is low instead of high. | Suitable where downstream logic requires active-low reset or enable assertion during power loss. | Select SI8652BB-B-IUR only if system design mandates low-default fail-safe behavior. |
| ADUM141E0BRZ | Four-channel, 100 Mbps max, SOIC-16 wide-body package; higher propagation delay (12 ns typ) and lower CMTI (35 kV/µs min). | Limited to four channels; lacks dual-enable control and failsafe configurability. | Choose ADUM141E0BRZ only when pin count and legacy footprint compatibility outweigh need for 150 Mbps and fail-safe flexibility. |
Compared with SI8652EB-B-IUR, SI8652BB-B-IUR provides identical timing and isolation but reverses fail-safe polarity, while ADUM141E0BRZ trades speed, channel count, and enable granularity for broader distributor availability and legacy design reuse.
Availability
SI8652EB-B-IUR is available at Aetrix Electronics and suitable for industrial automation systems, battery management systems, and isolated switch mode supplies requiring stable component supply, long-term lifecycle support, and automotive-grade traceability options.
Supply support for SI8652EB-B-IUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si865x family was designed specifically for high-reliability industrial and automotive isolation applications, emphasizing ultra-low power, precise timing, and reinforced safety certification across wide temperature ranges.
FAQ
What is the isolation rating and safety certification of SI8652EB-B-IUR?
SI8652EB-B-IUR provides 2.5 kVRMS isolation and is certified to UL 1577, CSA Component Notice 5A, VDE 0884-10, and CQC GB4943.1. These approvals validate its use in reinforced insulation applications per IEC 60950-1 and IEC 62368-1, making it suitable for industrial and automotive end equipment requiring functional safety compliance.
How does the fail-safe mode work on SI8652EB-B-IUR?
SI8652EB-B-IUR is configured at manufacture to assert logic high on all outputs when VDD1 is unpowered but VDD2 remains active. This behavior is hardwired via internal pull-ups and ensures downstream circuitry remains in a known safe state during primary-side power loss - critical for motor gate drivers and BMS fault signaling.
What are the supply voltage requirements for SI8652EB-B-IUR?
SI8652EB-B-IUR operates with independent 2.5–5.5 V supplies on both VDD1 and VDD2 rails. Each side requires a 0.1 µF bypass capacitor placed near the respective VDD/GND pins. The device functions correctly across the full –40 to +125 °C ambient range without derating.
Can SI8652EB-B-IUR support 150 Mbps data rates reliably?
Yes, SI8652EB-B-IUR guarantees 150 Mbps operation with 5 ns minimum pulse width and 350 ps peak eye diagram jitter. Its RF modulation scheme and 50 Ω output impedance enable clean signal integrity on controlled-impedance PCB traces, validated in eye diagrams per Figure 2.3 of the datasheet.
What is the purpose of EN1 and EN2 pins on SI8652EB-B-IUR?
EN1 controls the output state of A4 and A5, while EN2 controls B1, B2, and B3. When asserted high, each enables its assigned outputs to follow their respective inputs; when low, those outputs enter high-impedance. Both pins are internally pulled up to VDD2 (2 µA), allowing floating connection if unused - though external tie-off is recommended in noisy environments.
SI8652EB-B-IUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- No
- Number of Channels:
- 5
- Inputs - Side 1/Side 2:
- 3/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 50kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 4ns, 4ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI8652EB-B-IUR FAQ
1.How can I place an order for SI8652EB-B-IUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8652EB-B-IUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8652EB-B-IUR reliable?
The price and inventory of SI8652EB-B-IUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8652EB-B-IUR is usually 5 days.
3.What payment methods are accepted for SI8652EB-B-IUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8652EB-B-IUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8652EB-B-IUR?
SI8652EB-B-IUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8652EB-B-IUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8652EB-B-IUR?
For technical support, including SI8652EB-B-IUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8652EB-B-IUR requirements.
6.How does Aetrix verify that SI8652EB-B-IUR is sourced from the original manufacturer or authorized distributors?
All SI8652EB-B-IUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8652EB-B-IUR meets industry standards.
7.What is the process for return or replacement of SI8652EB-B-IUR?
All SI8652EB-B-IUR units undergo pre-shipment inspection (PSI). If there is an issue with SI8652EB-B-IUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8652EB-B-IUR part is unused and in its original packaging.
Return procedure for SI8652EB-B-IUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8652EB-B-IUR Tags
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ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

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ISO7720FDR
Texas Instruments

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ISO7721DR
Texas Instruments

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ISO7721FDR
Texas Instruments

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SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
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ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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