Skyworks Solutions Inc. SI8652ED-ASR
- Part No.:
- SI8652ED-ASR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8652ED-ASR.pdf
- Description:
- AUTOMOTIVE 5 KV 3 FORWARD & 2 RE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8652ED-ASR from Skyworks is a five-channel digital isolator with 3 input channels on VDD1 side and 2 output channels on VDD2 side, rated for 5 kVRMS reinforced insulation in wide-body SOIC-16 package. It supports DC–150 Mbps data rates, achieves <10 ns propagation delay, and features selectable high-default fail-safe mode, Schmitt-trigger inputs, and tri-state outputs via EN control - deployed in battery management systems and traction inverters requiring robust galvanic isolation.
For engineers reviewing the SI8652ED-ASR datasheet, SI8652ED-ASR pinout, SI8652ED-ASR application, or SI8652ED-ASR equivalent, this page delivers verified electrical specs, automotive-grade AEC-Q100 qualification status, fail-safe output behavior under power loss, and precise timing parameters including 0.5 ns channel-channel skew and 50 kV/µs CMTI - all confirmed for the exact SI8652ED-ASR variant.
Technical Context
The SI8652ED-ASR implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling stable operation from –40 to +125 °C. Its dual enable inputs (EN1 on VDD1 side, EN2 on VDD2 side) independently control A4/A5 and B1/B2/B3 outputs, supporting multiplexing and clock sync without external logic.
It integrates undervoltage lockout (UVLO) on both sides with 70 mV hysteresis, 50 Ω nominal output impedance, and failsafe default-high outputs configured at manufacture. All channels feature Schmitt-trigger inputs (0.44 V typical hysteresis) and operate across 2.5–5.5 V supply range on both sides.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5 kVRMS reinforced insulation - enables use in mains-connected BMS and EV traction inverters per IEC 62368-1 and IEC 60601-1. |
| Max Data Rate | 150 Mbps - supports high-speed CAN FD, SPI, and isolated ADC interface in real-time motor control loops. |
| Propagation Delay | 8.0 ns typical - ensures sub-10 ns timing alignment critical for gate driver synchronization in SiC/GaN inverters. |
| Channel-Channel Skew | 0.5 ns max - guarantees deterministic phase relationship between isolated feedback and control signals in multi-phase systems. |
| CMTI | 50 kV/µs min - maintains signal integrity during fast dv/dt transients in 800 V battery architectures. |
| Supply Range | 2.5–5.5 V on both VDD1 and VDD2 - allows direct interfacing with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Fail-Safe Mode | Default-high output state - ensures safe shutdown of downstream drivers when input-side power is lost in OBC or BMS applications. |
Pinout & Package
SI8652ED-ASR uses a RoHS-compliant 16-pin wide-body SOIC package (WB SOIC-16) with 8.0 mm creepage/clearance, certified for reinforced insulation up to 5 kVRMS per VDE 0884-10 and UL 1577.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side power supply | Supplies 2.5–5.5 V to transmitter side; UVLO threshold 2.24 V ensures clean startup in noisy automotive environments. |
| GND1 | Input-side ground reference | Reference for all Side A inputs and EN1; must be separated from GND2 by ≥8 mm PCB clearance for 5 kVRMS compliance. |
| A1–A3 | Input channels (Side A) | 3 unidirectional digital inputs with Schmitt-trigger thresholds (VT+ = 1.67 V, VT– = 1.23 V) for noise immunity in motor control feedback paths. |
| EN1 | Enable for A4/A5 outputs | Active-high control on VDD1 side; pulls up internally (2 µA), enabling hardware-gated isolation of auxiliary control signals. |
| A4, A5 | Input-controlled outputs (Side A) | Driven only when EN1 = high; used for bidirectional handshake or fault signaling across isolation barrier. |
| VDD2 | Output-side power supply | Supplies 2.5–5.5 V to receiver side; independent UVLO allows asymmetric power sequencing in isolated SMPS designs. |
| GND2 | Output-side ground reference | Reference for all Side B outputs and EN2; forms safety barrier with GND1 - requires reinforced insulation layout per IEC 60664-1. |
| B1–B3 | Output channels (Side B) | 3 unidirectional isolated outputs with 50 Ω impedance; drive 15 pF loads directly with 2.5 ns rise/fall times at 100 Mbps. |
| EN2 | Enable for B1–B3 outputs | Active-high control on VDD2 side; enables local tri-state control of isolated gate driver enable lines without cross-side signaling. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates optical degradation and startup delays; enables immediate data transmission after power-on with no initialization sequence required. |
| Selectable fail-safe output state | Factory-configured high-default mode ensures B1–B3 remain logic high during VDD1 loss - critical for safe disable of power stage drivers. |
| Dual independent enable inputs | EN1 controls A4/A5; EN2 controls B1–B3 - permits separate hardware gating of control and feedback paths in redundant BMS monitoring. |
| Automotive-grade AEC-Q100 qualification | Qualified to Grade 1 (–40 to +125 °C), with zero-defect manufacturing flow and AIAG-compliant PPAP documentation for EV system integration. |
| 50 kV/µs common-mode transient immunity | Prevents data corruption during 800 V bus switching events in traction inverters, exceeding ISO 7637-2 pulse 5b immunity requirements. |
Applications
| Battery Management System (BMS) | Traction Inverter Control |
|---|---|
|
Use Scenario: Isolating cell voltage monitoring ADC outputs and pack contactor control signals in 400–800 V EV battery packs. IC Role / Device Role / Timing Role: SI8652ED-ASR transmits isolated analog front-end data (A1–A3) and drives contactor enable lines (B1–B3) with <10 ns timing precision. Use Value: 5 kVRMS rating meets IEC 61000-4-5 surge immunity for Class 3B systems; default-high fail-safe prevents unintended contactor closure during MCU reset. |
Use Scenario: Providing isolated gate drive enable and current-sense feedback in three-phase SiC inverter modules. IC Role / Device Role / Timing Role: SI8652ED-ASR carries PWM enable (EN2 → B1–B3) and isolated shunt amplifier outputs (A1–A3) with 0.5 ns channel skew. Use Value: 50 kV/µs CMTI prevents false triggering during 100 V/ns dv/dt events; wide 2.5–5.5 V supply range interfaces directly with 3.3 V MCU and 5 V gate drivers. |
| On-Board Charger (OBC) | Industrial Motor Drive |
|
Use Scenario: Isolating digital control signals between AC/DC and DC/DC stages in bidirectional OBCs with 11–22 kW output. IC Role / Device Role / Timing Role: SI8652ED-ASR routes PFC enable (A1), LLC sync (A2), and fault flags (A3) to secondary-side controller while driving gate drivers (B1–B3). Use Value: AEC-Q100 qualification ensures reliability over 15-year vehicle lifetime; 150 Mbps rate supports high-resolution current loop sampling at 100 kHz. |
Use Scenario: Isolating encoder feedback and PWM command signals in servo drives for robotic arms and CNC machines. IC Role / Device Role / Timing Role: SI8652ED-ASR transmits quadrature encoder A/B/Z (A1–A3) and receives motion controller enable (B1–B3) with deterministic latency. Use Value: Sub-10 ns propagation delay enables 1 µs current loop update rates; Schmitt-trigger inputs reject EMI from nearby IGBT switching noise. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI8652BD-AS | Same 3:2 channel count and WB SOIC-16 package, but rated for 5 kVRMS with low-default fail-safe output. | Suitable where safe-off default is required instead of safe-on; identical timing and CMTI performance. | Select SI8652BD-AS if system safety logic requires outputs to go low upon input-side power loss. |
| ADUM141DBRZ | 4-channel isolator in narrow-body SOIC-16; 3.75 kVRMS rating, 100 Mbps max data rate, no dual-enable architecture. | Limited to lower-voltage industrial systems; lacks independent EN1/EN2 control and automotive qualification. | Choose ADUM141DBRZ only for cost-sensitive non-automotive designs where 3.75 kVRMS and single-enable suffice. |
Compared with SI8652ED-ASR, SI8652BD-AS provides identical isolation, speed, and package but reverses fail-safe polarity - making it a functional alternative where safety logic mandates low-default behavior. ADUM141DBRZ offers lower isolation and speed, lacks AEC-Q100, and cannot replicate dual-enable control, limiting its suitability to less demanding industrial contexts.
Availability
SI8652ED-ASR is available at Aetrix Electronics and suitable for battery management systems, traction inverters, on-board chargers, and industrial motor drives requiring stable component supply under automotive-grade quality and traceability protocols.
Supply support for SI8652ED-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for high-reliability applications.
The Si865x family was designed specifically for automotive and industrial isolation needs - delivering ultra-low-power, high-CMTI, AEC-Q100-qualified digital isolators with configurable fail-safe modes and reinforced 5 kVRMS insulation in standard SOIC packages.
FAQ
What is the isolation rating and safety certification status of SI8652ED-ASR?
SI8652ED-ASR is rated for 5 kVRMS reinforced isolation and certified to UL 1577, VDE 0884-10, CSA 5A, and CQC GB4943.1 standards. It meets IEC 62368-1 and IEC 60601-1 requirements for reinforced insulation, validated for continuous operation at working voltages up to 1350 VDC in automotive battery systems.
Does SI8652ED-ASR support fail-safe operation, and how is it configured?
Yes, SI8652ED-ASR has factory-configured default-high fail-safe mode. When VDD1 is unpowered but VDD2 remains active, outputs B1–B3 retain logic-high state. This behavior is fixed per ordering code ('ED' suffix denotes high-default); no external configuration is required or supported.
What are the supply voltage requirements for SI8652ED-ASR on both sides?
SI8652ED-ASR operates with independent 2.5–5.5 V supplies on VDD1 (input side) and VDD2 (output side). Each side includes undervoltage lockout with 2.24 V turn-on threshold and 70 mV hysteresis, allowing reliable operation across automotive battery voltage fluctuations and industrial SMPS outputs.
How does the dual-enable architecture of SI8652ED-ASR function in practice?
SI8652ED-ASR features EN1 (on VDD1 side) controlling A4/A5 outputs, and EN2 (on VDD2 side) controlling B1–B3 outputs. This allows independent hardware gating - for example, EN1 can enable auxiliary diagnostics while EN2 manages gate driver enables - without cross-isolation signaling or added logic gates.
Is SI8652ED-ASR qualified for automotive applications, and what does that entail?
Yes, SI8652ED-ASR is AEC-Q100 Grade 1 qualified (–40 to +125 °C), manufactured using full automotive process flows with zero-defect methodology, AIAG-compliant PPAP documentation, and IMDS/CAMDS material declarations - ensuring reliability for 15-year EV system lifetimes and compliance with OEM sourcing requirements.
SI8652ED-ASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- No
- Number of Channels:
- 5
- Inputs - Side 1/Side 2:
- 3/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8652ED-ASR FAQ
1.How can I place an order for SI8652ED-ASR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8652ED-ASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8652ED-ASR reliable?
The price and inventory of SI8652ED-ASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8652ED-ASR is usually 5 days.
3.What payment methods are accepted for SI8652ED-ASR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8652ED-ASR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8652ED-ASR?
SI8652ED-ASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8652ED-ASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8652ED-ASR?
For technical support, including SI8652ED-ASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8652ED-ASR requirements.
6.How does Aetrix verify that SI8652ED-ASR is sourced from the original manufacturer or authorized distributors?
All SI8652ED-ASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8652ED-ASR meets industry standards.
7.What is the process for return or replacement of SI8652ED-ASR?
All SI8652ED-ASR units undergo pre-shipment inspection (PSI). If there is an issue with SI8652ED-ASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8652ED-ASR part is unused and in its original packaging.
Return procedure for SI8652ED-ASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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