Skyworks Solutions Inc. SI8662BB-AS1R
- Part No.:
- SI8662BB-AS1R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI8662BB-AS1R.pdf
- Description:
- AUTOMOTIVE 2.5 KV 4 FORWARD & 2
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8662BB-AS1R from Skyworks is a six-channel digital isolator with 4 input channels on VDD1 side and 2 input channels on VDD2 side, delivering 150 Mbps data rate, <10 ns propagation delay, and 2.5 kVRMS isolation in a narrow-body SOIC-16 package. It features Schmitt-trigger inputs, selectable fail-safe low-default output, and operates across –40 to 125 °C for industrial and automotive isolated communication interfaces.
For engineers reviewing the SI8662BB-AS1R datasheet, SI8662BB-AS1R pinout, SI8662BB-AS1R application, or SI8662BB-AS1R equivalent, this page provides verified specifications, validated pin functions, real-world use cases in motor control and battery management, and confirmed alternative options for design-in and supply continuity.
Technical Context
The SI8662BB-AS1R implements RF-based on/off keying modulation across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its dual-supply architecture supports independent 2.5–5.5 V operation on both sides, with undervoltage lockout (UVLO) thresholds at 2.24 V (rising) and 2.16 V (falling) per side.
Each channel integrates Schmitt-trigger inputs for >0.44 V hysteresis, 50 Ω nominal output impedance, and precise timing: 8 ns typical propagation delay, 0.5 ns channel-channel skew, and 5 ns minimum pulse width. Fail-safe behavior defaults outputs low when VDD1 is unpowered and VDD2 remains active.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels & Direction | 6-channel, 4-input/2-output configuration across isolation barrier - enables asymmetric signal routing between controller and power stage |
| Max Data Rate | 150 Mbps - supports high-speed SPI, UART, and PWM feedback in real-time motor control loops |
| Propagation Delay | 5–13 ns (min–max), 8 ns typical - ensures sub-10 ns timing alignment critical for gate driver synchronization |
| Isolation Rating | 2.5 kVRMS - certified to UL 1577, VDE 0884-10, and IEC 62368-1 for reinforced insulation in industrial safety systems |
| Supply Voltage Range | 2.375–5.5 V per side - allows direct interface with 3.3 V microcontrollers and 5 V gate drivers without level-shifting |
| Fail-Safe Default | Low output state during VDD1 loss - prevents unintended high-side switch activation in power inverter fault conditions |
| CMTI | 50 kV/µs typical - maintains signal integrity under fast-switching dv/dt transients in SiC/GaN-based inverters |
Pinout & Package
SI8662BB-AS1R uses a RoHS-compliant narrow-body SOIC-16 package (5.3 mm width, 10.3 mm length) with 8.3 mm creepage and 8.0 mm clearance, rated for 2.5 kVRMS working voltage.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side power supply | Supplies 2.375–5.5 V to 4 input channels and transmitter circuitry; requires 0.1 µF bypass capacitor |
| GND1 | Input-side ground reference | Return path for VDD1; must be separated from GND2 by isolation barrier to maintain 2.5 kVRMS rating |
| INA1–INA4 | Input channels (side A) | Digital logic inputs with Schmitt-trigger thresholds (VT+ = 1.67 V, VT– = 1.23 V); tolerate 0–VDD1 range |
| VDD2 | Output-side power supply | Supplies 2.375–5.5 V to 2 output channels and receiver circuitry; independent of VDD1 |
| GND2 | Output-side ground reference | Return path for VDD2; galvanically isolated from GND1; defines output logic levels |
| OUTA1–OUTA2 | Output channels (side B) | CMOS-compatible outputs with 50 Ω impedance; drive 15 pF loads with 2.5–4.0 ns rise/fall times |
| NC | No-connect pins | Pins 9, 10, 15, and 16 are internally unused - must remain unconnected per datasheet guidance |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates LED aging and temperature drift issues of optocouplers; enables stable 60-year lifetime at rated voltage |
| Selectably fail-safe output | Factory-configured low-default state prevents hazardous output states during input-side power loss in safety-critical systems |
| Ultra-low power at 100 Mbps | 12.8 mA (typ) on VDD1 and 19.4 mA (typ) on VDD2 at 100 Mbps - reduces thermal load in dense PCB layouts |
| High CMTI immunity | 50 kV/µs common-mode transient immunity - sustains reliable operation in high-dv/dt environments like traction inverters |
| Automotive qualification | AEC-Q100 Grade 1 qualified (–40 to 125 °C) with AIAG-compliant PPAP documentation support |
Applications
| Motor Control Systems | Battery Management Systems |
|---|---|
Use Scenario: Isolating PWM signals and current-sense feedback between MCU and three-phase inverter gate drivers in industrial servo drives. IC Role / Device Role / Timing Role: Six-channel isolator providing 4x PWM inputs and 2x analog-to-digital converter (ADC) status outputs across isolation barrier. Use Value: Sub-10 ns propagation delay ensures synchronized switching of high-side and low-side FETs, minimizing shoot-through risk. | Use Scenario: Signal isolation between cell monitoring ICs and system controller in high-voltage EV battery packs. IC Role / Device Role / Timing Role: Transfers voltage/current telemetry and fault alerts across 2.5 kVRMS barrier while maintaining fail-safe low default on communication lines. Use Value: AEC-Q100 qualification and 125 °C operation ensure reliability in under-hood battery pack environments. |
| Industrial PLC I/O Modules | Isolated Switch-Mode Power Supplies |
Use Scenario: Digital input conditioning and output driving in programmable logic controller backplanes with mixed 24 V DC field and 3.3 V logic domains. IC Role / Device Role / Timing Role: Provides 4-channel isolated digital input sensing and 2-channel isolated output actuation with Schmitt-trigger noise rejection. Use Value: 0.44 V input hysteresis rejects EMI-induced glitches in electrically noisy factory floors. | Use Scenario: Feedback isolation for secondary-side voltage regulation and primary-side gate drive enable/disable in isolated DC-DC converters. IC Role / Device Role / Timing Role: Transmits error amplifier output and soft-start signals across isolation barrier with precise timing and low power consumption. Use Value: 1.6 mA/channel at 1 Mbps enables energy-efficient operation in always-on standby power stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM161N0BRZ-RL7 | 6-channel, 150 Mbps, 2.5 kVRMS, SOIC-16 NB; failsafe default not configurable - fixed high or low per variant | Requires separate part number selection for fail-safe polarity; lacks AEC-Q100 automotive qualification | Preferred where fixed fail-safe polarity suffices and automotive compliance is not required |
| ISO6762FDWR | 6-channel, 50 Mbps max, 5 kVRMS, SOIC-16 WB; higher isolation but lower speed and no fail-safe option | Used where enhanced creepage (>8.5 mm) and 5 kVRMS are mandatory, but 150 Mbps is unnecessary | Chosen when reinforced insulation and long-term reliability outweigh need for high-speed data transfer |
Compared with ADUM161N0BRZ-RL7 and ISO6762FDWR, SI8662BB-AS1R uniquely combines 150 Mbps speed, factory-configurable fail-safe low default, AEC-Q100 qualification, and 2.5 kVRMS in narrow-body SOIC-16 - making it optimal for space-constrained automotive and industrial real-time control designs requiring guaranteed safe-state behavior.
Availability
SI8662BB-AS1R is available at Aetrix Electronics and suitable for industrial automation systems, battery management systems, and motor control applications requiring stable component supply, automotive-grade reliability, and long-term lifecycle support.
Supply support for SI8662BB-AS1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies.
The Si866x family is engineered for high-reliability galvanic isolation in harsh environments, targeting industrial automation, medical electronics, and automotive electrification systems demanding precision timing and safety certification.
FAQ
What is the isolation rating and safety certification of SI8662BB-AS1R?
SI8662BB-AS1R provides 2.5 kVRMS isolation and is certified to UL 1577, VDE 0884-10, CSA Component Notice 5A, and IEC 62368-1 for reinforced insulation. These approvals validate its use in safety-critical industrial and automotive systems where galvanic separation is mandated by end-equipment standards.
Does SI8662BB-AS1R require external components for basic operation?
Yes - SI8662BB-AS1R requires a 0.1 µF ceramic bypass capacitor between VDD1 and GND1, and another between VDD2 and GND2, placed as close as possible to the device pins. No pull-up/pull-down resistors are needed, as Schmitt-trigger inputs and fail-safe logic are integrated.
How does the fail-safe mode function in SI8662BB-AS1R?
In SI8662BB-AS1R, the fail-safe mode defaults all outputs low when VDD1 is unpowered and VDD2 remains active. This behavior is factory-set (denoted by "BB" in the part number) and prevents unsafe high-side switch activation during input-side power faults in motor drives and power supplies.
What is the maximum operating temperature range for SI8662BB-AS1R?
SI8662BB-AS1R operates from –40 to 125 °C ambient temperature and is AEC-Q100 Grade 1 qualified. Its electrical parameters - including propagation delay, supply current, and CMTI - remain stable across this full range, supporting deployment in engine compartments and industrial enclosures.
Can SI8662BB-AS1R interface directly with 3.3 V and 5 V logic systems?
Yes - SI8662BB-AS1R supports independent 2.375–5.5 V supplies on both sides, allowing direct connection to 3.3 V microcontrollers on VDD1 and 5 V gate drivers on VDD2. Input thresholds (VT+ = 1.67 V, VT– = 1.23 V) and CMOS-compatible outputs ensure interoperability without level shifters.
SI8662BB-AS1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 4/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8662BB-AS1R FAQ
1.How can I place an order for SI8662BB-AS1R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8662BB-AS1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8662BB-AS1R reliable?
The price and inventory of SI8662BB-AS1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8662BB-AS1R is usually 5 days.
3.What payment methods are accepted for SI8662BB-AS1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8662BB-AS1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8662BB-AS1R?
SI8662BB-AS1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8662BB-AS1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8662BB-AS1R?
For technical support, including SI8662BB-AS1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8662BB-AS1R requirements.
6.How does Aetrix verify that SI8662BB-AS1R is sourced from the original manufacturer or authorized distributors?
All SI8662BB-AS1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8662BB-AS1R meets industry standards.
7.What is the process for return or replacement of SI8662BB-AS1R?
All SI8662BB-AS1R units undergo pre-shipment inspection (PSI). If there is an issue with SI8662BB-AS1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8662BB-AS1R part is unused and in its original packaging.
Return procedure for SI8662BB-AS1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8662BB-AS1R Tags
-
ISO1212DBQR
Texas Instruments

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ISO6721BDR
Texas Instruments

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SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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