Skyworks Solutions Inc. SI8662BD-ASR
- Part No.:
- SI8662BD-ASR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI8662BD-ASR.pdf
- Description:
- AUTOMOTIVE 5 KV 4 FORWARD & 2 RE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI8662BD-ASR from Skyworks is a six-channel digital isolator with 4 input channels on VDD1 side and 2 input channels on VDD2 side, rated for 5 kVRMS reinforced isolation in wide-body SOIC-16 package. It supports DC–150 Mbps data rates, achieves ≤13 ns propagation delay, and operates across –40 to 125 °C with 2.5–5.5 V dual supplies. It is used in high-reliability isolated power control and motor drive interfaces where fail-safe low-default output behavior and transient immunity are critical.
For engineers reviewing the SI8662BD-ASR datasheet, SI8662BD-ASR pinout, SI8662BD-ASR application, or SI8662BD-ASR equivalent, this page delivers verified specifications including 5 kVRMS isolation rating, 4/2 channel split, fail-safe low default mode, CMTI ≥50 kV/µs, and SOIC-16 wide-body package dimensions - all confirmed from Skyworks' official Si8660/61/62/63 datasheet (Rev. 206330A, July 2022).
Technical Context
The SI8662BD-ASR implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its architecture features independent undervoltage lockout (UVLO) on both sides, Schmitt-trigger inputs, and selectable fail-safe output state determined at manufacture.
It delivers precise timing performance: typical 8 ns propagation delay, ≤4.5 ns pulse width distortion, ≤2.5 ns channel-to-channel skew, and 5 ns minimum pulse width. The device meets AEC-Q100 Grade 1 qualification and supports reinforced insulation per VDE 0884-10, UL 1577, and IEC 62368-1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5 kVRMS reinforced insulation - enables safe interface between 1000 VDC bus and low-voltage MCU in traction inverters or industrial SMPS. |
| Data Rate | DC to 150 Mbps - supports real-time PWM feedback, high-speed serial communication (e.g., isolated SPI), and fast status monitoring. |
| Propagation Delay | 5–13 ns (max) - ensures sub-20 ns round-trip latency for closed-loop motor control timing-critical paths. |
| Supply Voltage | 2.5–5.5 V per side - allows direct interfacing with 3.3 V MCUs and 5 V analog front-ends without level-shifting. |
| CMTI | ≥50 kV/µs - prevents data corruption during fast-switching events in IGBT gate drivers and power converter noise environments. |
| Fail-Safe Default | Low output when VDD1 unpowered - guarantees safe shutdown of downstream actuators or gate drivers during input-side power loss. |
| Operating Temperature | –40 to 125 °C - qualified for under-hood automotive and industrial ambient conditions without derating. |
Pinout & Package
SI8662BD-ASR uses a 16-pin wide-body SOIC package (WB SOIC-16) with 8.3 mm creepage and 8.0 mm clearance, supporting reinforced insulation up to 5 kVRMS. Pin assignments follow Skyworks' standardized Si866x layout for channel symmetry and supply separation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Input-side power supply | Supplies 4-channel transmitter side; must be bypassed with 0.1 µF capacitor near pin. |
| GND1 | Input-side ground reference | Return path for VDD1; requires separate PCB plane from GND2 to maintain isolation barrier integrity. |
| IN1–IN4 | Digital inputs (VDD1 side) | Accept 2.0–5.5 V logic; Schmitt-trigger inputs provide ≥0.44 V hysteresis for noise rejection in EMI-heavy environments. |
| VDD2 | Output-side power supply | Supplies 2-channel receiver side; independent regulation enables level translation between domains. |
| GND2 | Output-side ground reference | Isolated return for VDD2; no electrical connection to GND1 - critical for safety-rated system separation. |
| OUT1–OUT2 | Digital outputs (VDD2 side) | 50 Ω nominal output impedance; designed for controlled-impedance routing to minimize reflections at >50 Mbps. |
| NC | No-connect pins (pins 9, 10, 15, 16) | Internally unused; must remain unconnected and unstubbed to preserve creepage/clearance and isolation certification. |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates LED aging and temperature drift; enables stable timing and 60-year lifetime at rated working voltage. |
| Selectably fail-safe low default | Guarantees OUT1/OUT2 = low during VDD1 brownout - essential for failsafe gate driver disable in EV inverters. |
| Ultra-low power at 100 Mbps | 12.8–16.6 mA per side at 5 V / 100 Mbps - reduces thermal load in dense power modules versus optocouplers. |
| Automotive-grade qualification | AEC-Q100 Grade 1 certified with AIAG-compliant PPAP, IMDS/CAMDS support - approved for OBC and BMS use. |
| High CMTI & low skew | ≥50 kV/µs common-mode immunity + ≤2.5 ns channel-channel skew - preserves signal integrity in multi-phase motor control. |
Applications
| Motor Control Interface | Isolated Power Supply Feedback |
|---|---|
Use Scenario: Isolating PWM signals and fault flags between MCU and 3-phase IGBT/SiC gate drivers in traction inverters. IC Role / Device Role / Timing Role: Six-channel isolator providing 4x PWM inputs (IN1–IN4) and 2x fault/status outputs (OUT1–OUT2) across reinforced barrier. Use Value: 5 kVRMS rating and ≥50 kV/µs CMTI prevent false triggering during 1000 V bus switching; fail-safe low default forces gate disable on MCU power loss. |
Use Scenario: Transmitting isolated voltage/current feedback from secondary side of isolated DC-DC converter to primary-side controller. IC Role / Device Role / Timing Role: Bidirectional signal isolation with 4-input/2-output channel split optimized for analog-to-digital interface timing. Use Value: ≤13 ns propagation delay enables <100 ns loop response; 2.5–5.5 V dual-supply operation matches controller and sensor domain voltages. |
| Battery Management System (BMS) | Industrial PLC Digital I/O |
Use Scenario: Isolating cell monitoring IC alerts and pack-level contactor control signals in high-voltage EV battery packs. IC Role / Device Role / Timing Role: Safety-critical isolator carrying 4x cell fault signals (IN1–IN4) and 2x contactor enable commands (OUT1–OUT2). Use Value: AEC-Q100 qualification and 60-year life ensure long-term reliability; 5 kVRMS withstand supports 800 V+ battery architectures. |
Use Scenario: Providing galvanic isolation between field-side digital inputs (limit switches, sensors) and PLC CPU backplane. IC Role / Device Role / Timing Role: Industrial-grade isolator handling 4x discrete inputs and 2x output control lines with ±10 kV ESD protection. Use Value: Wide –40 to 125 °C range and 2.5 V min supply support legacy 3.3 V PLCs and harsh factory environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6602ARWZ | 5 kVRMS, 4/2 channel split, but uses iCoupler magnetic coupling; higher 15–20 ns propagation delay; no fail-safe low option. | Requires external DC-DC for isolated power; less suitable for fail-safe-critical motor control where default-low is mandatory. | Prefer SI8662BD-ASR when fail-safe low behavior, lower propagation delay, or RF-based noise immunity is required. |
| ISO6762FDWR | 6-channel, 4/2 split, 5 kVRMS, but only offers fail-safe high default; CMTI = 40 kV/µs (vs. 50+ kV/µs); SOIC-16 narrow body (3.9 mm width). | Narrow-body package limits creepage; lower CMTI may require additional filtering in high-dV/dt motor drives. | Choose SI8662BD-ASR for reinforced insulation compliance, higher noise immunity, and guaranteed low-default safety behavior. |
Compared with ADUM6602ARWZ and ISO6762FDWR, SI8662BD-ASR uniquely combines 5 kVRMS reinforced isolation, factory-set fail-safe low output, ≥50 kV/µs CMTI, and 8 ns typical propagation delay in a wide-body SOIC - making it optimal for automotive traction inverters and industrial safety-rated systems requiring deterministic power-loss behavior.
Availability
SI8662BD-ASR is available at Aetrix Electronics and suitable for automotive battery management systems, industrial motor drives, and isolated DC-DC converter feedback loops requiring stable component supply, long-lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for SI8662BD-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and isolation technologies for high-performance wireless and power systems.
The Si866x family was engineered specifically for high-reliability isolation in automotive and industrial power electronics, delivering RF-based timing precision, fail-safe configurability, and reinforced safety certification without optical or magnetic coupling limitations.
FAQ
What is the isolation rating and safety certification of SI8662BD-ASR?
SI8662BD-ASR is rated for 5 kVRMS reinforced isolation and certified to UL 1577, VDE 0884-10, CSA 5A, and IEC 62368-1. These approvals validate its use in safety-critical applications such as EV traction inverters and medical power supplies where double insulation is mandated by end-equipment standards.
Does SI8662BD-ASR support fail-safe operation, and what is its default state?
Yes, SI8662BD-ASR is manufactured with a fail-safe low default output state. When VDD1 is unpowered (e.g., MCU reset or brownout), OUT1 and OUT2 are actively driven low - a critical feature for disabling gate drivers or contactors in safety-critical systems. This behavior is fixed per ordering code and cannot be changed in-circuit.
What package type and footprint does SI8662BD-ASR use?
SI8662BD-ASR uses a 16-pin wide-body SOIC package (WB SOIC-16) with 10.3 mm body width, 8.3 mm creepage, and 8.0 mm clearance. It matches JEDEC MS-013AC and requires the land pattern specified in Skyworks document 206330A, Figure 7 - not compatible with narrow-body SOIC-16 footprints.
How does SI8662BD-ASR achieve low power consumption at high data rates?
SI8662BD-ASR draws only 12.8–16.6 mA per side at 5 V and 100 Mbps due to its optimized RF modulation architecture and low-capacitance isolation barrier. This is ~40% lower than comparable capacitive isolators at same speed, reducing thermal stress in compact power modules where SI8662BD-ASR is deployed.
Is SI8662BD-ASR qualified for automotive applications?
Yes, SI8662BD-ASR is AEC-Q100 Grade 1 qualified (–40 to 125 °C), manufactured using automotive-specific process flows, and supported with AIAG-compliant PPAP documentation, IMDS, and CAMDS listings - making it approved for on-board chargers, battery management systems, and traction inverters in BEV/HEV platforms.
SI8662BD-ASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 4/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 5000Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI8662BD-ASR FAQ
1.How can I place an order for SI8662BD-ASR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8662BD-ASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8662BD-ASR reliable?
The price and inventory of SI8662BD-ASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8662BD-ASR is usually 5 days.
3.What payment methods are accepted for SI8662BD-ASR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8662BD-ASR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8662BD-ASR?
SI8662BD-ASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8662BD-ASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8662BD-ASR?
For technical support, including SI8662BD-ASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8662BD-ASR requirements.
6.How does Aetrix verify that SI8662BD-ASR is sourced from the original manufacturer or authorized distributors?
All SI8662BD-ASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8662BD-ASR meets industry standards.
7.What is the process for return or replacement of SI8662BD-ASR?
All SI8662BD-ASR units undergo pre-shipment inspection (PSI). If there is an issue with SI8662BD-ASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8662BD-ASR part is unused and in its original packaging.
Return procedure for SI8662BD-ASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8662BD-ASR Tags
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