My Inquiry
My Account
Skyworks Solutions Inc. SI8662EB-AUR
- Part No.:
- SI8662EB-AUR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SI8662EB-AUR.pdf
- Description:
- AUTOMOTIVE 2.5 KV 4 FORWARD & 2
- Quantity:
- Payment:
- Shipping:
Inventory:1,694
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI8662EB-AUR from Skyworks is a six-channel digital isolator with 4 input channels on VDD1 side and 2 output channels on VDD2 side, supporting up to 150 Mbps data rate, <10 ns propagation delay, and 5 kVRMS reinforced isolation in a wide-body SOIC-16 package. It operates from 2.5–5.5 V supplies, features Schmitt-trigger inputs, selectable high-default fail-safe mode, and is AEC-Q100 qualified for automotive battery management systems.
For engineers reviewing the SI8662EB-AUR datasheet, SI8662EB-AUR pinout, SI8662EB-AUR application, or SI8662EB-AUR equivalent, this page delivers verified electrical specs, fail-safe behavior under undervoltage, CMTI immunity (50 kV/µs), channel skew (≤2.5 ns), and package-specific creepage/clearance compliance per IEC 60950-1 and VDE 0884-10.
Technical Context
The SI8662EB-AUR implements RF-based on/off keying across a semiconductor isolation barrier-eliminating LED aging and startup initialization. Its dual-supply architecture (VDD1/VDD2) enables galvanic separation between controller and power stage domains, with independent UVLO monitoring per side ensuring robust fault response during asymmetric power sequencing.
All six channels use identical RF modulation/demodulation circuitry, with precise timing control delivering ≤1.5 ns pulse width distortion and ≤0.5 ns channel-to-channel skew. The high-default fail-safe mode is implemented via internal pull-ups on all outputs, activated when VDD1 is unpowered while VDD2 remains active.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 150 Mbps - supports high-speed SPI, CAN FD, and isolated ADC interfaces without oversampling or retiming. |
| Propagation Delay | 5.0–13 ns - ensures deterministic timing in motor gate driver feedback loops and real-time control systems. |
| Channel-Channel Skew | ≤2.5 ns - maintains phase alignment across multi-channel PWM or encoder signal isolation. |
| Common-Mode Transient Immunity | 50 kV/µs - suppresses noise coupling in high-dV/dt environments like traction inverters and SMPS. |
| Isolation Rating | 5 kVRMS - meets reinforced insulation requirements per IEC 62368-1 and VDE 0884-10 for 8 mm creepage. |
| Supply Voltage Range | 2.5–5.5 V - interoperable with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Fail-Safe Default | High - outputs remain logic-high during VDD1 loss, enabling safe shutdown of downstream power stages. |
Pinout & Package
SI8662EB-AUR is housed in a RoHS-compliant 16-pin wide-body SOIC package (WB SOIC-16) with 8.0 mm creepage distance, certified for reinforced insulation up to 5 kVRMS. This package meets IPC-7351B standards and supports JEDEC J-STD-020 reflow profiles (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | VDD1-side Inputs | Four isolated digital inputs referenced to VDD1/GND1; accept 2.0–5.5 V logic levels with Schmitt-trigger hysteresis. |
| 5, 6 | VDD2-side Outputs | Two isolated digital outputs referenced to VDD2/GND2; drive 50 Ω loads with 0.2–0.4 V VOL at 4 mA sink. |
| 7, 14 | GND1 / GND2 | Separate ground references for primary and secondary sides; must not be connected externally. |
| 8, 15 | VDD1 / VDD2 | Independent 2.5–5.5 V supplies; each monitored by dedicated UVLO circuit with 70 mV hysteresis. |
| 9–13 | No Connect (NC) | Internally unused pins; must be left floating or tied to GND per layout guidelines to minimize EMI. |
Key Features
| Feature | Design Value |
|---|---|
| RF-Based Isolation | Eliminates LED degradation and startup delay-enables immediate data transmission after power-on without handshake or calibration. |
| 50 kV/µs CMTI | Prevents false triggering in high-noise motor drives and inverters where fast-switching SiC/GaN devices generate large dV/dt transients. |
| High-Default Fail-Safe | Ensures active-high enable signals (e.g., to IGBT gate drivers) default to OFF state during primary-side power loss-critical for functional safety. |
| Ultra-Low Power @ 100 Mbps | 12.8–16.6 mA per side at 100 Mbps (5 V), reducing thermal load in densely packed automotive ECUs and BMS modules. |
| AEC-Q100 Grade 1 | Qualified for –40 °C to +125 °C operation with zero-defect manufacturing flow-meets ASIL-B system-level requirements. |
Applications
| Battery Management System (BMS) | On-Board Charger (OBC) |
|---|---|
Use Scenario: Isolating cell voltage monitoring ADCs and pack contactor control signals in 400–800 V EV battery packs. IC Role / Device Role / Timing Role: Six-channel isolator separates MCU domain (VDD1) from high-voltage sensing/control domain (VDD2), providing 5 kVRMS reinforced insulation and <10 ns timing fidelity for SOC estimation algorithms. Use Value: Enables accurate, noise-immune voltage sampling at 150 Mbps while maintaining ASIL-B compliance via fail-safe high-default outputs during MCU brownout. |
Use Scenario: Galvanically isolating bidirectional AC/DC control signals between grid-side PFC controller and DC-link inverter stage. IC Role / Device Role / Timing Role: SI8662EB-AUR carries PWM commands and fault feedback across isolation barrier with ≤2.5 ns channel skew to synchronize interleaved bridge legs. Use Value: Supports 100+ kHz switching frequencies with sub-ns jitter control, reducing EMI and improving power density in compact OBC designs. |
| Traction Inverter Control | Industrial Motor Drive |
Use Scenario: Isolating gate driver enable/disable signals and DESAT feedback from SiC half-bridge modules operating at >1000 V bus voltage. IC Role / Device Role / Timing Role: Provides 5 kVRMS reinforced insulation and 50 kV/µs CMTI to prevent false turn-on during high-dV/dt commutation events. Use Value: Ensures reliable gate drive signal integrity even under worst-case 50 kV/µs transients-reducing field failure rates in BEV powertrains. |
Use Scenario: Isolating encoder quadrature signals and PWM outputs in servo drives requiring functional safety certification. IC Role / Device Role / Timing Role: SI8662EB-AUR routes four position feedback channels and two direction/enable signals across isolation barrier with matched propagation delay. Use Value: Maintains encoder phase accuracy (<2.5 ns skew) for precise torque control in ISO 13849 PLd-rated machinery. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6602ARWZ | 5-channel, 25 Mbps max rate, integrated isolated DC-DC converter, 3.75 kVRMS rating | Lower data rate limits use in high-speed SPI or encoder interfaces; integrated power simplifies supply design | Choose ADUM6602ARWZ when isolated power is needed and data rate ≤25 Mbps suffices |
| ISO6762FDWR | 6-channel, 100 Mbps max rate, 5 kVRMS, failsafe low default, SOIC-16 WB package | Lacks AEC-Q100 qualification and 150 Mbps capability; lower CMTI (42 kV/µs) | Choose ISO6762FDWR for industrial motor drives where AEC-Q100 is unnecessary and 100 Mbps meets timing needs |
Compared with ADUM6602ARWZ and ISO6762FDWR, SI8662EB-AUR uniquely combines AEC-Q100 Grade 1 qualification, 150 Mbps speed, 50 kV/µs CMTI, and high-default fail-safe in a 5 kVRMS wide-body SOIC-making it optimal for automotive traction and charging systems demanding both performance and safety certification.
Availability
SI8662EB-AUR is available at Aetrix Electronics and suitable for battery management systems, on-board chargers, traction inverters, and industrial motor drives requiring stable component supply across automotive and industrial temperature ranges.
Supply support for SI8662EB-AUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.
The Si866x family was designed specifically for high-reliability automotive and industrial isolation-delivering RF-based digital isolation with AEC-Q100 qualification, reinforced 5 kVRMS ratings, and fail-safe operation for functional safety-critical systems.
FAQ
What is the isolation rating and safety certification status of SI8662EB-AUR?
SI8662EB-AUR provides 5 kVRMS reinforced isolation and is certified to UL 1577, VDE 0884-10, CSA 5A, IEC 62368-1, and GB4943.1. It meets reinforced insulation requirements for 8 mm creepage in wide-body SOIC packaging and is AEC-Q100 Grade 1 qualified for automotive use from –40 °C to +125 °C.
Does SI8662EB-AUR require external components for stable operation?
Yes-SI8662EB-AUR requires a 0.1 µF ceramic bypass capacitor placed as close as possible between each VDD pin (pins 8 and 15) and its respective ground (pins 7 and 14). No pull-up/pull-down resistors are needed, as the high-default fail-safe mode uses internal pull-ups on all outputs.
How does the fail-safe mode operate in SI8662EB-AUR during power loss?
In SI8662EB-AUR, the fail-safe mode defaults outputs to logic-high when VDD1 is unpowered but VDD2 remains active. This behavior is hardwired via internal pull-ups and ensures downstream power stages (e.g., IGBT gate drivers) remain disabled during MCU-side brownout-supporting ASIL-B functional safety goals.
What is the maximum achievable data rate and associated timing performance of SI8662EB-AUR?
SI8662EB-AUR supports up to 150 Mbps with typical propagation delay of 8.0 ns, pulse width distortion of 1.5 ns, and channel-to-channel skew of 0.5 ns. These values are guaranteed over –40 °C to +125 °C and enable precise timing in high-speed isolated communication links such as SPI and digital encoder interfaces.
Can SI8662EB-AUR be used in systems requiring IEC 61000-4-5 surge protection?
SI8662EB-AUR itself is not a surge protection device, but its 5 kVRMS isolation rating and 50 kV/µs CMTI make it suitable for placement behind properly designed transient voltage suppression circuits (e.g., TVS diodes and common-mode chokes) in IEC 61000-4-5 Level 3/4 compliant systems like EV chargers and industrial drives.
SI8662EB-AUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 6
- Inputs - Side 1/Side 2:
- 4/2
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 35kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13ns, 13ns
- Pulse Width Distortion (Max):
- 4.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.375V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QSOP
SI8662EB-AUR FAQ
1.How can I place an order for SI8662EB-AUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI8662EB-AUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI8662EB-AUR reliable?
The price and inventory of SI8662EB-AUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI8662EB-AUR is usually 5 days.
3.What payment methods are accepted for SI8662EB-AUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI8662EB-AUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI8662EB-AUR?
SI8662EB-AUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI8662EB-AUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI8662EB-AUR?
For technical support, including SI8662EB-AUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI8662EB-AUR requirements.
6.How does Aetrix verify that SI8662EB-AUR is sourced from the original manufacturer or authorized distributors?
All SI8662EB-AUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI8662EB-AUR meets industry standards.
7.What is the process for return or replacement of SI8662EB-AUR?
All SI8662EB-AUR units undergo pre-shipment inspection (PSI). If there is an issue with SI8662EB-AUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI8662EB-AUR part is unused and in its original packaging.
Return procedure for SI8662EB-AUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI8662EB-AUR Tags
-
ISO1212DBQR
Texas Instruments
-
ISO6721BDR
Texas Instruments
-
SI8710AC-B-ISR
Skyworks Solutions Inc.
-
ISO7720FDR
Texas Instruments
-
ISO7721DR
Texas Instruments
-
ISO7721FDR
Texas Instruments
-
SI8710CC-B-ISR
Skyworks Solutions Inc.
-
ISO6741FQDWRQ1
Texas Instruments
-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments
-
ISO7741DWR
Texas Instruments
-
ISO7741FDWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
