Skyworks Solutions Inc. SI86S602AC-ASR

Overview

SI86S602AC-ASR from Skyworks Solutions is a bidirectional I²C isolator with one bidirectional I²C channel (SDA) and one unidirectional non-I²C channel (SCL), housed in an SOIC-8 narrow-body package. It provides 3.75 kV_RMS galvanic isolation, supports I²C bus speeds up to 1.7 MHz, features open-drain outputs with 35 mA sink capability, and operates across –40 °C to +125 °C for industrial and automotive applications including battery management systems and isolated digital power communications.

For engineers reviewing the SI86S602AC-ASR datasheet, SI86S602AC-ASR pinout, SI86S602AC-ASR application, or SI86S602AC-ASR equivalent, key selection considerations include its AEC-Q100 qualification, 3.75 kV_RMS isolation rating, dual-supply operation (3.0–5.5 V), anti-latch bidirectional SDA architecture, and compatibility with standard I²C pull-up resistor networks without external components.

Technical Context

The SI86S602AC-ASR implements Skyworks' proprietary RF-based isolation technology-replacing optical coupling with modulated RF carriers across a semiconductor barrier-to achieve lower propagation delay, higher EMI immunity, and stable performance over temperature and lifetime. Its bidirectional SDA channel uses asymmetric logic thresholds (V_OL,A > V_IL,A) to prevent latch-up, while the unidirectional SCL channel operates as a standard CMOS-compatible digital isolator with 10 Mbps data rate support.

Each side (A and B) has independent undervoltage lockout (UVLO) circuitry, enabling robust hot-swap operation and safe behavior during asymmetric power sequencing. The device maintains Hi-Z output states on powered sides when the opposite side loses supply, preventing bus contention in mixed-power-domain I²C systems.

Key Specifications

Pinout & Package

SI86S602AC-ASR is packaged in an 8-pin narrow-body SOIC (SOIC-8 NB) with creepage/clearance optimized for 3.75 kV_RMS working voltage. Pin functions are validated per Skyworks Si860x datasheet Section 6.1 and Figure 3.3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C isolator applications.

Compared with ADUM1250ARZ and ISO1540DR, SI86S602AC-ASR uniquely combines AEC-Q100 qualification, 1.7 MHz I²C speed, and a dedicated unidirectional SCL channel-making it the only option suitable for high-speed automotive BMS and PoE-PD applications demanding reinforced insulation and production-part approval.

Availability

SI86S602AC-ASR is available at Aetrix Electronics and suitable for battery management systems, isolated digital power supply communications, and Power over Ethernet applications requiring stable component supply, long-term lifecycle support, and automotive-grade traceability.

Supply support for SI86S602AC-ASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and isolation technologies for high-reliability applications.

The SI860x family-including SI86S602AC-ASR-is engineered specifically for galvanic isolation of I²C and SMBus interfaces in harsh environments, with emphasis on automotive, industrial, and PoE systems demanding AEC-Q100 compliance and reinforced insulation.

FAQ

What is the maximum I²C bus frequency supported by SI86S602AC-ASR?

SI86S602AC-ASR supports I²C bus speeds up to 1.7 MHz, meeting Fast-Mode Plus (Fm+) specifications. This is confirmed in Table 5.3 of the Skyworks Si860x datasheet, where F_max is specified as 1.7 MHz under all operating conditions (3.0–5.5 V, –40 °C to +125 °C). The device achieves this using low-propagation-delay RF isolation and anti-latch SDA architecture-enabling reliable clock stretching and ACK timing without external components. SI86S602AC-ASR maintains this speed across its full voltage and temperature range.

Does SI86S602AC-ASR require external components for basic I²C isolation?

No, SI86S602AC-ASR requires only standard I²C pull-up resistors (typically 1–3 kΩ) on both SDA and SCL lines-no external anti-latch circuits, level shifters, or bias networks are needed. Its integrated asymmetric logic thresholds (V_OL,A > V_IL,A) inherently prevent bus latching, and its open-drain outputs directly interface with standard I²C drivers. Per Section 3.2 and Figure 3.3 of the Si860x datasheet, the solution is single-chip and self-contained-reducing design complexity and PCB footprint versus discrete optocoupler-based approaches.

Is SI86S602AC-ASR qualified for automotive applications?

Yes, SI86S602AC-ASR is AEC-Q100 qualified (Grade 1, –40 °C to +125 °C) and built using automotive-specific manufacturing flows, including AIAG-compliant PPAP documentation, IMDS/CAMDS material listings, and zero-defect methodology throughout production. The "-A" suffix in the part number confirms automotive grade per Table 1.1 of the datasheet. It is explicitly listed for on-board chargers, battery management systems, and traction inverters-validating its suitability for ASIL-B–capable systems in hybrid and battery electric vehicles.

What isolation rating does SI86S602AC-ASR provide, and which safety standards does it meet?

SI86S602AC-ASR provides 3.75 kV_RMS galvanic isolation for 1 minute, certified to UL 1577, CSA Component Notice 5A, VDE EN 60747-5-5, and CQC GB4943.1. It satisfies reinforced insulation requirements per IEC 60950-1, IEC 61010-1, and IEC 60601-1. These certifications are documented in the Safety Regulatory Approvals section of the Si860x datasheet and verified via third-party test reports-ensuring compliance for end-equipment certification in industrial, medical, and automotive applications.

How does SI86S602AC-ASR handle power loss on one side during operation?

When power is lost on either side (e.g., AVDD = 0 V), SI86S602AC-ASR places the corresponding I²C outputs into high-impedance (Hi-Z) state-preventing bus contention and ensuring the powered side retains full control. This behavior is defined in Table 4.1 (Si86xx Operation Table) and enables safe hot-swap operation. For example, if Side A loses power while Side B remains active, BSDA and BSCL go Hi-Z, allowing the B-side master to continue communicating with downstream slaves without interference-critical for redundant power architectures in PoE and BMS systems.