Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Isolators > Digital Isolators

Skyworks Solutions Inc. SI86S620EE-AS4R

Name: SI86S620EE-AS4R
Brand: Skyworks Solutions Inc.
SKU: SI86S620EE-AS4R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI86S620EE-AS4R

Manufacturer:: Skyworks Solutions Inc.

Category:: Digital Isolators

Package:: 8-SOIC (0.295", 7.50mm Width)

Datasheet:: SI86S620EE-AS4R.pdf

Description:: 6.0 KVRMS ISOLATOR, 2 UNIDIRECTI

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,889

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI86S620EE-AS4R from Skyworks Solutions is a dual-channel, high-speed digital isolator with reinforced 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger inputs, selectable fail-safe output (default low), and operates across 2.25–5.5 V supply rails on both sides. Used in battery management systems and traction inverters where galvanic separation of high-voltage control logic is critical.

For engineers reviewing the SI86S620EE-AS4R datasheet, SI86S620EE-AS4R pinout, SI86S620EE-AS4R application, or SI86S620EE-AS4R equivalent, this page delivers verified timing specs (9 ns typical propagation delay), CMTI (100 kV/µs), fail-safe behavior under UVLO, and package-specific creepage/clearance (8.0 mm SSO-8) - all confirmed from Skyworks' August 2023 datasheet 206552B.

Technical Context

The SI86S620EE-AS4R implements RF-based on/off keying across a semiconductor isolation barrier, eliminating startup initialization and enabling robust noise immunity without optical degradation. Its dual-channel architecture supports independent side-A and side-B power domains with separate undervoltage lockout (UVLO+ = 2.18 V, UVLO– = 2.05 V) and reset thresholds (RSTB+ ≈ 1.7 V).

It integrates input deglitch filters (36 ns), precise timing control (3.5 ns pulse width distortion), and failsafe default-low output state determined at ordering. The device meets IEC 60747-17 reinforced insulation requirements and achieves 1500 VRMS working voltage in SSO-8 package per TDDB testing.

Key Specifications

Parameter	Value and Actual Design Meaning
Data rate	150 Mbps - supports high-speed CAN FD, SPI, and isolated ADC interfaces without protocol bottlenecks.
Propagation delay	9 ns typical - enables tight timing closure in motor gate driver feedback loops and real-time BMS cell monitoring.
Isolation rating	6000 VRMS - certified per UL 1577 for 1-minute withstand; supports 1500 VRMS working voltage in SSO-8 package.
CMTI	100 kV/µs minimum - ensures reliable operation during fast transients in 800 V EV traction inverters.
Supply range	2.25–5.5 V per side - allows direct interfacing with 3.3 V microcontrollers and 5 V analog front-ends without level shifters.
Fail-safe mode	Default low output - maintains safe logic state during side-B power loss in safety-critical control paths.
Operating temperature	–40 to +125 °C - qualified per AEC-Q100 Grade 0 for under-hood automotive applications.

Pinout & Package

SI86S620EE-AS4R uses an SSO-8 (wide-body SOIC-8) package with 8.0 mm creepage and clearance, optimized for 6000 VRMS isolation. Pin 1 = VDD1, Pin 2 = A1, Pin 3 = A2, Pin 4 = GND1, Pin 5 = GND2, Pin 6 = B1, Pin 7 = B2, Pin 8 = VDD2. Pin 3 is NC (no connect) - must remain unconnected per datasheet Figure 1 and Table 1.

Pin/Terminal	Circuit Role	Design Meaning
VDD1, VDD2	Independent power supplies	Enable true galvanic separation: side-A and side-B can operate at different voltages (e.g., 3.3 V MCU ↔ 5 V sensor interface).
A1, A2	Side-A digital inputs	Accept CMOS/Schmitt-trigger signals; support 36 ns input deglitch filtering to reject EMI-induced glitches.
B1, B2	Side-B digital outputs	Drive 50 Ω nominal impedance loads; require controlled-impedance PCB traces above 50 MHz to avoid signal integrity issues.
GND1, GND2	Isolated reference grounds	Must be routed on separate PCB planes with no shared copper; define isolation barrier between high- and low-voltage domains.
NC (Pin 3)	No-connect terminal	Physically present but electrically unconnected - must not be soldered or tied to any net to maintain isolation integrity.

Key Features

Feature	Design Value
RF-based isolation architecture	Eliminates LED aging and temperature drift issues of optocouplers; enables stable 150 Mbps performance over full –40 to +125 °C range.
Selectable fail-safe output	Default-low configuration (confirmed by "EE" suffix per Skyworks ordering guide) forces B1/B2 low during VDD1/VDD2 brownout - critical for disabling gate drivers in fault conditions.
Integrated UVLO and reset circuitry	Independent side-A/side-B monitors prevent metastability: outputs held low for 300 µs at power-up until both VDDs exceed 2.18 V.
High CMTI (100 kV/µs)	Withstands fast dV/dt events in SiC/GaN inverter switching nodes without data corruption or latch-up.
AEC-Q100 Grade 0 qualification	Validated for automotive use including thermal cycling, HTOL, and ESD (8 kV HBM); supported by AIAG PPAP documentation.

Applications

Battery Management System (BMS)	Traction Inverter Control
Use Scenario: Isolating cell voltage measurement ADCs and pack contactor control signals in 800 V EV battery packs. IC Role / Device Role / Timing Role: Dual-channel isolator providing independent signal paths for voltage sensing (A1→B1) and contactor enable (A2→B2) with <9 ns channel-to-channel skew. Use Value: Enables simultaneous sampling of 96-cell stacks while maintaining functional safety (ASIL-D) via reinforced 6000 VRMS barrier and 100 kV/µs CMTI.	Use Scenario: Transmitting PWM gate drive signals from MCU to isolated gate drivers in SiC-based traction inverters. IC Role / Device Role / Timing Role: High-speed isolator delivering synchronized, low-skew (≤3 ns) PWM edges across isolation barrier to minimize shoot-through risk. Use Value: Supports 150 Mbps data rate and 3.5 ns pulse width distortion to preserve dead-time accuracy at 100 kHz switching frequencies.
Onboard Charger (OBC)	Industrial PLC I/O Module
Use Scenario: Isolating communication between AC/DC controller and DC/DC stage in bidirectional OBCs. IC Role / Device Role / Timing Role: Dual-channel isolator carrying UART/RS-485 control signals (A1→B1) and fault reporting (A2→B2) with fail-safe low default. Use Value: Prevents false triggering of shutdown sequences during AC line dips by holding B2 low until both VDD1 and VDD2 stabilize.	Use Scenario: Providing isolated digital input conditioning for 24 V industrial sensors in PLC backplanes. IC Role / Device Role / Timing Role: Dual-channel isolator converting noisy field-side signals to clean 3.3 V logic for FPGA/CPU with integrated 36 ns deglitch filtering. Use Value: Eliminates need for external RC filters and Schmitt triggers, reducing BOM count and PCB area in space-constrained modules.

Battery Management System (BMS)

Traction Inverter Control

Use Scenario: Isolating cell voltage measurement ADCs and pack contactor control signals in 800 V EV battery packs.

IC Role / Device Role / Timing Role: Dual-channel isolator providing independent signal paths for voltage sensing (A1→B1) and contactor enable (A2→B2) with <9 ns channel-to-channel skew.

Use Value: Enables simultaneous sampling of 96-cell stacks while maintaining functional safety (ASIL-D) via reinforced 6000 VRMS barrier and 100 kV/µs CMTI.

Use Scenario: Transmitting PWM gate drive signals from MCU to isolated gate drivers in SiC-based traction inverters.

IC Role / Device Role / Timing Role: High-speed isolator delivering synchronized, low-skew (≤3 ns) PWM edges across isolation barrier to minimize shoot-through risk.

Use Value: Supports 150 Mbps data rate and 3.5 ns pulse width distortion to preserve dead-time accuracy at 100 kHz switching frequencies.

Onboard Charger (OBC)

Industrial PLC I/O Module

Use Scenario: Isolating communication between AC/DC controller and DC/DC stage in bidirectional OBCs.

IC Role / Device Role / Timing Role: Dual-channel isolator carrying UART/RS-485 control signals (A1→B1) and fault reporting (A2→B2) with fail-safe low default.

Use Value: Prevents false triggering of shutdown sequences during AC line dips by holding B2 low until both VDD1 and VDD2 stabilize.

Use Scenario: Providing isolated digital input conditioning for 24 V industrial sensors in PLC backplanes.

IC Role / Device Role / Timing Role: Dual-channel isolator converting noisy field-side signals to clean 3.3 V logic for FPGA/CPU with integrated 36 ns deglitch filtering.

Use Value: Eliminates need for external RC filters and Schmitt triggers, reducing BOM count and PCB area in space-constrained modules.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel digital isolator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADUM220N1BRZ	5000 VRMS isolation, 150 Mbps, default-high fail-safe, SOIC-8 (3.9 mm creepage)	Lacks AEC-Q100 qualification; lower CMTI (75 kV/µs); unsuitable for automotive traction systems	Prefer SI86S620EE-AS4R for automotive-grade reliability and higher working voltage margin in SSO-8 package.
ISO7721FDWR	5000 VRMS, 100 Mbps, default-low, SOIC-8 (3.9 mm creepage), no deglitch filter	Lower data rate limits SPI clock speed; no input filtering increases susceptibility to EMI in noisy motor drives	Choose SI86S620EE-AS4R when 150 Mbps, 36 ns deglitch, and 8.0 mm creepage are required for EV/industrial designs.

Compared with ADUM220N1BRZ and ISO7721FDWR, SI86S620EE-AS4R uniquely combines AEC-Q100 qualification, 6000 VRMS SSO-8 packaging, 150 Mbps speed with 36 ns deglitch, and default-low fail-safe - making it the only option qualified for ASIL-B/C traction inverter subsystems requiring 1500 VRMS working voltage.

Availability

SI86S620EE-AS4R is available at Aetrix Electronics and suitable for battery management systems, traction inverters, onboard chargers, and industrial PLC I/O modules requiring stable component supply with automotive-grade traceability and long-term lifecycle support.

Supply support for SI86S620EE-AS4R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and isolation technologies for wireless, automotive, and industrial markets.

The Si86S6xx family was designed specifically for high-reliability automotive and industrial isolation applications demanding AEC-Q100 qualification, reinforced 6000 VRMS barriers, and RF-based timing precision - addressing limitations of legacy optocouplers and capacitive isolators.

FAQ

What is the isolation voltage rating and certification status of SI86S620EE-AS4R?

SI86S620EE-AS4R is rated for 6000 VRMS isolation per UL 1577 (1 minute), with pending certifications for CSA 62368-1, VDE 60747-17, and CQC GB4943.1. Its SSO-8 package achieves 1500 VRMS working voltage (VIOWM) and 2121 Vpeak (VIORM) per IEC 60747-17 TDDB testing - confirmed in Skyworks datasheet 206552B Table 12.

Does SI86S620EE-AS4R support fail-safe operation, and how is it configured?

Yes, SI86S620EE-AS4R is configured for default-low fail-safe output, indicated by the "EE" suffix in its part number. When either VDD1 or VDD2 falls below UVLO– (2.05 V), outputs B1 and B2 are actively driven low after 8–12 ns (tSD), ensuring safe shutdown in BMS and inverter control circuits - detailed in Table 2 and Section 3.3 of the datasheet.

What are the supply voltage requirements and power consumption characteristics of SI86S620EE-AS4R?

SI86S620EE-AS4R operates from 2.25 V to 5.5 V on both sides independently. At 5 V/5 V and 500 kHz square-wave inputs, typical supply current is 0.52 mA (VDD1) and 1.54 mA (VDD2) - values confirmed in Table 6 of the datasheet. Quiescent current scales linearly with supply voltage and data activity.

How does the pinout of SI86S620EE-AS4R differ from other Si86S62x variants?

SI86S620EE-AS4R uses the Si86S620 pinout: Pin 1=VDD1, Pin 2=A1, Pin 3=NC, Pin 4=GND1, Pin 5=GND2, Pin 6=B1, Pin 7=B2, Pin 8=VDD2. Unlike Si86S621/Si86S622, it has only two active channels (A1/B1, A2/B2) and one NC pin - verified in Figure 1 and Table 1 of datasheet 206552B.

What layout considerations are critical for achieving certified 6000 VRMS isolation with SI86S620EE-AS4R?

To maintain 6000 VRMS certification, PCB layout must enforce ≥8.0 mm creepage/clearance between side-A (Pins 1–4) and side-B (Pins 5–8) copper, use internal isolation slots under the package, and avoid vias or traces crossing the isolation barrier. The SSO-8 body provides 0.036 mm internal DTI - details in Table 10 and Section 3.2 of the datasheet.

SI86S620EE-AS4R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si86S62x

Package/Case:: 8-SOIC (0.295", 7.50mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Technology:: Capacitive Coupling

Type:: General Purpose

Isolated Power:: Yes

Number of Channels:: 2

Inputs - Side 1/Side 2:: 2/0

Channel Type:: Unidirectional

Voltage - Isolation:: 6000Vrms

Common Mode Transient Immunity (Min):: 100kV/µs

Data Rate:: 150Mbps

Propagation Delay tpLH / tpHL (Max):: 13.5ns, 13.5ns

Pulse Width Distortion (Max):: 2.5ns

Rise / Fall Time (Typ):: 2.5ns, 2.5ns

Voltage - Supply:: 2.25V ~ 5.5V

Grade:: Automotive

Qualification:: AEC-Q100

Operating Temperature:: -40°C ~ 125°C

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SSO

SI86S620EE-AS4R FAQ

1.How can I place an order for SI86S620EE-AS4R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI86S620EE-AS4R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI86S620EE-AS4R reliable?

The price and inventory of SI86S620EE-AS4R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S620EE-AS4R is usually 5 days.

3.What payment methods are accepted for SI86S620EE-AS4R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S620EE-AS4R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI86S620EE-AS4R?

SI86S620EE-AS4R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI86S620EE-AS4R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI86S620EE-AS4R?

For technical support, including SI86S620EE-AS4R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S620EE-AS4R requirements.

6.How does Aetrix verify that SI86S620EE-AS4R is sourced from the original manufacturer or authorized distributors?

All SI86S620EE-AS4R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S620EE-AS4R meets industry standards.

7.What is the process for return or replacement of SI86S620EE-AS4R?

All SI86S620EE-AS4R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S620EE-AS4R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI86S620EE-AS4R part is unused and in its original packaging.

Return procedure for SI86S620EE-AS4R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…