Skyworks Solutions Inc. SI86S621EE-AS4R
- Part No.:
- SI86S621EE-AS4R
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 8-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SI86S621EE-AS4R.pdf
- Description:
- 6.0 KVRMS ISOLATOR, 2 UNIDIRECTI
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI86S621EE-AS4R from Skyworks Solutions is a dual-channel, high-speed digital isolator with reinforced 6000 VRMS isolation, 150 Mbps data rate, and AEC-Q100 qualification for automotive systems. It features Schmitt-trigger + CMOS inputs, selectable fail-safe output (default low), and operates across 2.25–5.5 V supply rails. Used in battery management systems and traction inverters where galvanic separation and noise immunity are critical.
For engineers reviewing the SI86S621EE-AS4R datasheet, SI86S621EE-AS4R pinout, SI86S621EE-AS4R application, or SI86S621EE-AS4R equivalent, key selection criteria include its 10 ns typical propagation delay, 100 kV/µs CMTI, -40 to +125 °C operation, and SSO-8 package with 8.0 mm creepage/clearance - all validated for automotive-grade isolated signal transmission.
Technical Context
The SI86S621EE-AS4R implements RF-based on/off keying across a semiconductor isolation barrier, eliminating start-up initialization and enabling robust noise immunity without optical degradation. Its dual-channel architecture supports independent side-A (VDD1/GND1) and side-B (VDD2/GND2) power domains with UVLO and reset circuitry per side.
It integrates input deglitch filters (36 ns), precise timing control (3.5 ns pulse width distortion), and failsafe logic that holds outputs low during VDD1 loss while VDD2 remains active. The device meets IEC 60747-17 reinforced insulation requirements with 1500 VRMS working voltage in SSO-8 packaging.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | 150 Mbps - supports high-speed CAN FD, SPI, and isolated ADC/DAC interfaces without protocol bottlenecks |
| Propagation delay | 5–14 ns (typ. 10 ns) - enables tight timing closure in motor control PWM feedback loops |
| Pulse width distortion | ≤4.5 ns - preserves duty cycle integrity for precision timing-critical applications like gate drive signaling |
| CMTI | 100 kV/µs - rejects fast transients in high-noise environments such as onboard chargers and inverters |
| Isolation rating | 6000 VRMS (1 min) - certified per UL 1577, VDE 60747-17, and CSA 62368-1 for reinforced insulation |
| Supply range | 2.25–5.5 V - interoperable with 3.3 V and 5 V logic domains on both sides without level shifters |
| Operating temperature | –40 to +125 °C - qualified per AEC-Q100 Grade 0 for under-hood automotive use |
Pinout & Package
SI86S621EE-AS4R uses an SSO-8 (wide-body SOIC-8) package with 8.0 mm creepage and clearance, optimized for 6000 VRMS isolation. Pin 1 = VDD1, Pin 2 = A1, Pin 3 = A2, Pin 4 = GND1, Pin 5 = GND2, Pin 6 = B1, Pin 7 = B2, Pin 8 = VDD2. Pins labeled NC are not internally connected and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1 | Side A power supply | Provides 2.25–5.5 V bias for input-side logic and RF transmitter; requires 0.1 µF + 10 µF bypass capacitors |
| A1, A2 | Side A digital I/O | Dual-channel inputs with Schmitt-trigger + CMOS thresholds; support 36 ns deglitch filtering |
| GND1 | Side A ground | Reference return for VDD1 domain; must be separated from GND2 by ≥8.0 mm PCB spacing |
| GND2 | Side B ground | Reference return for VDD2 domain; forms isolation barrier boundary with GND1 |
| B1, B2 | Side B digital I/O | Dual-channel outputs with 50 Ω nominal impedance; default-low fail-safe state when VDD1 is unpowered |
| VDD2 | Side B power supply | Provides 2.25–5.5 V bias for output-side logic and RF receiver; independent of VDD1 |
Key Features
| Feature | Design Value |
|---|---|
| RF-based isolation architecture | Eliminates LED aging and temperature drift; enables zero-startup initialization and stable 150 Mbps operation over full temperature range |
| Selectable fail-safe mode (default low) | Ensures safe system state during input-side power loss - e.g., forces gate driver disable in traction inverter fault conditions |
| 36 ns input deglitch filter | Rejects EFT bursts and switching noise below 28 MHz, preventing false triggering in noisy industrial bus lines |
| 100 kV/µs CMTI | Withstands rapid common-mode transients induced by IGBT switching in 800 V battery systems without data corruption |
| AEC-Q100 Grade 0 qualification | Validated for continuous operation at +125 °C ambient, supporting placement near power modules in EV drivetrains |
Applications
| Battery Management System (BMS) | Traction Inverter Control |
|---|---|
Use Scenario: Isolating cell voltage monitoring signals from high-voltage battery stacks (up to 900 V) to MCU-side ADCs. IC Role / Device Role / Timing Role: Dual-channel digital isolator transmitting sampled analog front-end data with <10 ns channel-to-channel skew. Use Value: Enables accurate SOC estimation via 150 Mbps isolated SPI communication while maintaining 6000 VRMS reinforced insulation per UL 1577. | Use Scenario: Transmitting PWM gate drive commands from controller to isolated half-bridge drivers in 800 V electric vehicle inverters. IC Role / Device Role / Timing Role: Fail-safe dual-channel isolator delivering synchronized, low-skew (≤3 ns) signals to upper/lower IGBT gates. Use Value: Guarantees safe shutdown (default-low output) during controller power loss, preventing shoot-through in high-power stages. |
| Onboard Charger (OBC) | Industrial PLC I/O Module |
Use Scenario: Isolating digital control signals between AC/DC and DC/DC stages in bidirectional OBCs operating up to 10 kW. IC Role / Device Role / Timing Role: High-CMTI dual isolator interfacing microcontroller GPIOs with secondary-side feedback controllers. Use Value: Maintains signal integrity amid 100+ kV/µs transients generated by SiC MOSFET switching, reducing need for external filtering. | Use Scenario: Providing channel-isolated digital input conditioning for 24 V DC field sensors in factory automation cabinets. IC Role / Device Role / Timing Role: Dual-channel isolator with Schmitt-trigger inputs rejecting line noise on long sensor cables. Use Value: Eliminates optocoupler replacement cycles and supports hot-swap I/O expansion with 2.25–5.5 V flexible supply compatibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM220N1BRZ | 5000 VRMS isolation; 150 Mbps; 10 ns propagation delay; SOIC-8 (narrow-body, 3.9 mm creepage) | Lacks AEC-Q100 qualification and 6000 VRMS rating; unsuitable for automotive traction systems | Preferred for cost-sensitive industrial PLCs where 5000 VRMS suffices and layout space is constrained |
| ISO7721DWR | 5000 VRMS; 100 Mbps; 11 ns propagation delay; SOIC-8 (narrow-body); no deglitch filter | Lower CMTI (85 kV/µs); no fail-safe option; not AEC-Q100 qualified | Suitable for non-automotive isolated UART or I²C links where lower data rate and reduced noise immunity are acceptable |
Compared with ADUM220N1BRZ and ISO7721DWR, SI86S621EE-AS4R delivers higher isolation (6000 vs. 5000 VRMS), automotive qualification, integrated 36 ns deglitching, and guaranteed default-low fail-safe behavior - making it uniquely suited for safety-critical EV powertrain subsystems requiring reinforced insulation and deterministic fault response.
Availability
SI86S621EE-AS4R is available at Aetrix Electronics and suitable for battery management systems, traction inverters, and onboard chargers requiring stable component supply with automotive-grade reliability and long-term lifecycle support.
Supply support for SI86S621EE-AS4R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.
The Si86S6xx family targets high-reliability isolated communication in automotive electrification and industrial automation, with design emphasis on AEC-Q100 compliance, 6000 VRMS reinforcement, and RF-based noise immunity.
FAQ
What is the isolation voltage rating of SI86S621EE-AS4R and which standards does it meet?
SI86S621EE-AS4R is rated for 6000 VRMS isolation per UL 1577 (1 minute), with reinforced insulation certification per VDE 60747-17 (2121 Vpeak), CSA 62368-1, and GB4943.1. Its SSO-8 package provides 8.0 mm creepage and clearance, enabling compliance with IEC 60664-1 for up to 1000 VRMS mains voltage applications. SI86S621EE-AS4R achieves this rating without external components or layout modifications beyond standard high-voltage spacing rules.
Does SI86S621EE-AS4R support fail-safe operation, and how is it configured?
Yes, SI86S621EE-AS4R implements a selectable fail-safe mode where outputs default to logic low when VDD1 is unpowered but VDD2 remains active. This behavior is fixed at manufacture (not user-configurable) and is indicated by the "E" suffix in the part number. SI86S621EE-AS4R uses internal pull-downs on B1/B2 outputs, ensuring safe deactivation of downstream drivers during controller-side power faults - critical in traction inverter gate control.
What is the maximum data rate and propagation delay of SI86S621EE-AS4R?
SI86S621EE-AS4R supports up to 150 Mbps data rate with a typical propagation delay of 10 ns and a maximum of 14 ns over –40 to +125 °C. These values are guaranteed under VDD = 2.5–5.5 V and CL = 15 pF loading. SI86S621EE-AS4R maintains this performance without requiring external termination resistors due to its 50 Ω nominal output impedance, simplifying high-speed PCB routing.
How does SI86S621EE-AS4R handle power supply sequencing and undervoltage conditions?
SI86S621EE-AS4R features independent UVLO and reset circuits on both sides: VDD1 UVLO threshold is 2.10–2.25 V (rising), and VDD2 operates identically. Below UVLO, outputs enter a 100 kΩ pulldown state for ≤300 µs startup time. If VDD1 drops below ~1.7 V, a full reset reloads device configuration. SI86S621EE-AS4R tolerates asynchronous power-up of VDD1 and VDD2 without latch-up or data corruption.
Is SI86S621EE-AS4R compatible with 3.3 V and 5 V logic systems on both sides?
Yes, SI86S621EE-AS4R operates across 2.25–5.5 V on both VDD1 and VDD2 rails, enabling direct interface with 3.3 V MCUs and 5 V peripheral logic without level shifters. Input thresholds scale with VDDx (VIH = 0.7×VDDx, VIL = 0.3×VDDx), and output drive strength (VOH/VOL) is specified across the full range. SI86S621EE-AS4R maintains 150 Mbps performance at both 3.3 V and 5 V supplies, as verified in Tables 6 and 7 of the datasheet.
SI86S621EE-AS4R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si86S62x
- Package/Case:
- 8-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- General Purpose
- Isolated Power:
- Yes
- Number of Channels:
- 2
- Inputs - Side 1/Side 2:
- 1/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 100kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 13.5ns, 13.5ns
- Pulse Width Distortion (Max):
- 2.5ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SSO
SI86S621EE-AS4R FAQ
1.How can I place an order for SI86S621EE-AS4R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S621EE-AS4R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S621EE-AS4R reliable?
The price and inventory of SI86S621EE-AS4R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S621EE-AS4R is usually 5 days.
3.What payment methods are accepted for SI86S621EE-AS4R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S621EE-AS4R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S621EE-AS4R?
SI86S621EE-AS4R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S621EE-AS4R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S621EE-AS4R?
For technical support, including SI86S621EE-AS4R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S621EE-AS4R requirements.
6.How does Aetrix verify that SI86S621EE-AS4R is sourced from the original manufacturer or authorized distributors?
All SI86S621EE-AS4R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S621EE-AS4R meets industry standards.
7.What is the process for return or replacement of SI86S621EE-AS4R?
All SI86S621EE-AS4R units undergo pre-shipment inspection (PSI). If there is an issue with SI86S621EE-AS4R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S621EE-AS4R part is unused and in its original packaging.
Return procedure for SI86S621EE-AS4R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S621EE-AS4R Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
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