Skyworks Solutions Inc. SI86S631EC-AS1
- Part No.:
- SI86S631EC-AS1
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Digital Isolators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SI86S631EC-AS1.pdf
- Description:
- 3.75 KVRMS ISOLATOR, 3 UNIDIRECT
- Quantity:
- Payment:

- Shipping:

Inventory:1,699
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI86S631EC-AS1 from Skyworks Solutions is a 3-channel, reinforced digital isolator with bidirectional signal isolation across an integrated semiconductor barrier. It delivers DC–150 Mbps data rate, 10 ns typical propagation delay, and 6000 VRMS isolation rating in a WB SOIC-16 package. Designed for isolated ADC/DAC interfaces and motor control gate drivers in industrial inverters.
For engineers reviewing the SI86S631EC-AS1 datasheet, SI86S631EC-AS1 pinout, SI86S631EC-AS1 application, or SI86S631EC-AS1 equivalent, key selection criteria include fail-safe output configuration (default-low), AEC-Q100 qualification, IEC 60747-17 reinforced insulation, and tri-state enable support for bus sharing in high-noise power electronics systems.
Technical Context
The SI86S631EC-AS1 implements RF-based on/off keying modulation across its isolation barrier-eliminating startup initialization and enabling deterministic timing behavior. Its dual-side undervoltage lockout (UVLO) with independent RSTB reset thresholds (1.7 V) ensures robust power sequencing in asymmetric supply environments.
Each channel integrates Schmitt-trigger inputs with 0.15×VDD hysteresis and CMOS-compatible thresholds, supporting 2.25–5.5 V operation on both sides. The device features side-specific enable pins (EN1/EN2) for tri-state output control and supports selectable default-low fail-safe mode per ordering option.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | DC to 150 Mbps - enables high-speed serial links such as isolated SPI clock domains or fast feedback loops in digital power controllers. |
| Propagation delay | 10 ns typical - ensures tight timing alignment between isolated control and sensing paths in motor drive PWM generation. |
| Isolation rating | 6000 VRMS - meets reinforced insulation requirements per UL 1577 and IEC 60747-17 for >1000 VAC working voltage systems. |
| Supply range | 2.25–5.5 V per side - allows interoperability with 3.3 V microcontrollers and 5 V analog front-ends without level shifters. |
| Fail-safe mode | Default-low output - guarantees safe shutdown state during input-side power loss in isolated gate driver applications. |
| CMTI | 100 kV/µs minimum - prevents false triggering under fast transient common-mode noise in inverter switching nodes. |
| Operating temperature | –40 to +125 °C - supports deployment in under-hood automotive BMS and industrial motor drives without derating. |
Pinout & Package
SI86S631EC-AS1 is housed in a wide-body SOIC-16 (WB SOIC-16) package with creepage/clearance optimized for 6000 VRMS reinforced insulation. Pin layout follows the Si86S63x family configuration with three isolated channels, dual-side enable, and dedicated ground/supply pins per side.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | A1, A2, A3 | Side A digital inputs/outputs - connect to MCU GPIO or controller-side logic; support Schmitt-trigger noise immunity. |
| 4 | VDD1 | Side A power supply - requires 0.1 µF + 10 µF bypass capacitors placed adjacent to pin for stable high-speed operation. |
| 5 | GND1 | Side A ground reference - must be routed separately from GND2 to maintain isolation integrity and minimize coupling. |
| 6 | NC | No connect - internally unconnected; no external connection permitted. |
| 7–9 | B1, B2, B3 | Side B digital inputs/outputs - interface with isolated peripherals (e.g., ADC, gate driver ICs); electrically separated from Side A. |
| 10 | EN2 | Side B output enable - active-high control for tri-stating all B-side outputs during bus arbitration or fault conditions. |
| 11 | GND2 | Side B ground reference - forms isolated return path; must not share PCB copper with GND1. |
| 12 | VDD2 | Side B power supply - independently regulated supply required; decoupling identical to VDD1. |
| 13 | GND1 | Second Side A ground - duplicate ground pin for improved high-frequency return path; tied to same net as Pin 5. |
| 14 | HF | High-frequency test point - internal RF transmitter/receiver monitoring node; not for user connection. |
| 15, 16 | XMTR / RCVR | RF modulation/demodulation terminals - internal RF circuit nodes; no external access or routing allowed. |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced IEC 60747-17 rating | Validated barrier performance for safety-critical systems requiring dual-redundant insulation, including medical and EV traction inverters. |
| Tri-state outputs with EN1/EN2 | Enables shared-bus topologies (e.g., isolated SPI daisy chains) by allowing multiple devices to coexist on one physical bus without contention. |
| Selectable default-low fail-safe | Guarantees B-side outputs go low during A-side power loss - critical for disabling gate drivers in isolated half-bridge configurations. |
| No start-up initialization | Eliminates boot-time delays and configuration sequences; outputs become valid within 0.3 ms of VDD crossing UVLO+ threshold. |
| AEC-Q100 qualified | Qualified to Grade 1 (–40 to +125 °C) with automotive-grade process flow, PPAP documentation, and IMDS/CAMDS compliance support. |
Applications
| Industrial Motor Control | Isolated ADC Interface |
|---|---|
|
Use Scenario: Gate driving for 3-phase IGBT/SiC modules in variable-frequency drives with ±1500 VDC bus voltage. IC Role / Device Role / Timing Role: Isolates PWM signals from MCU to gate driver IC while maintaining <10 ns propagation matching across all 3 channels. Use Value: Prevents shoot-through faults during power-up/down via default-low fail-safe and withstands 100 kV/µs CMTI at switching node dv/dt. |
Use Scenario: Digitally isolating 16-bit sigma-delta ADC outputs in precision current/voltage sensing for servo amplifiers. IC Role / Device Role / Timing Role: Transfers serialized ADC data across isolation barrier with 150 Mbps capability and sub-ns pulse width distortion. Use Value: Maintains measurement accuracy by eliminating ground loop noise and enabling independent analog/digital domain grounding. |
| Onboard Charger (OBC) | Battery Management System (BMS) |
|
Use Scenario: Isolating communication between AC/DC controller and DC/DC secondary-side regulation in 11 kW EV OBCs. IC Role / Device Role / Timing Role: Provides bidirectional UART or SPI isolation with side-specific enable control for firmware updates and status reporting. Use Value: Meets reinforced insulation requirements (UL 62368-1, IEC 60601-1) and supports 125 °C ambient operation near power stages. |
Use Scenario: Isolating cell voltage monitor ICs from main BMS microcontroller in 800 V battery packs. IC Role / Device Role / Timing Role: Transfers precise voltage readings and fault alerts across barrier with guaranteed timing predictability and no initialization delay. Use Value: Enables functional safety compliance (ISO 26262 ASIL-B) through certified 6000 VRMS isolation and AEC-Q100 qualification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital isolator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM3301ARWZ | 3-channel, 25 Mbps max, 2500 VRMS, SOIC-16 (narrow body), no AEC-Q100 qualification | Suitable for non-automotive industrial control where lower data rate and reduced isolation voltage are acceptable | Choose when cost sensitivity outweighs need for 150 Mbps or 6000 VRMS; verify layout clearance for 2500 VRMS vs. 6000 VRMS system requirements |
| ISO6731FDWR | 3-channel, 50 Mbps max, 5000 VRMS, SOIC-16 (wide body), AEC-Q100 Grade 1, no selectable fail-safe mode | Applicable in automotive BMS where 50 Mbps suffices and fixed default state is acceptable | Prefer when existing TI ecosystem integration is prioritized; note absence of programmable fail-safe may require external pull-downs |
Compared with ADUM3301ARWZ and ISO6731FDWR, SI86S631EC-AS1 provides the highest data rate (150 Mbps) and strongest isolation (6000 VRMS), plus AEC-Q100 qualification and configurable fail-safe - making it optimal for next-generation EV power electronics demanding timing precision and safety certification.
Availability
SI86S631EC-AS1 is available at Aetrix Electronics and suitable for industrial motor control, onboard chargers, and battery management systems requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for SI86S631EC-AS1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in high-performance analog semiconductors, specializing in RF, timing, and isolation technologies for communications, automotive, and industrial markets.
The Si86S6xx family was engineered specifically for high-reliability, high-speed digital isolation in safety-critical power conversion and automotive electrification systems - emphasizing reinforced insulation, ultra-low propagation skew, and AEC-Q100 compliance.
FAQ
What is the isolation voltage rating of SI86S631EC-AS1 and which safety standards does it meet?
SI86S631EC-AS1 is rated for 6000 VRMS isolation per UL 1577 for 1 minute and carries reinforced insulation certification per IEC 60747-17. It also meets CSA 62368-1 and 60601-1, and CQC GB4943.1 - making SI86S631EC-AS1 suitable for medical and industrial equipment requiring double insulation barriers.
Does SI86S631EC-AS1 require power-on initialization or configuration before operation?
No. SI86S631EC-AS1 uses RF-based on/off keying and requires no startup initialization sequence. Outputs become valid within 0.3 ms after VDD crosses the UVLO+ threshold (2.18 V typical), and the device enters normal operation immediately - a key advantage over optocoupler-based or capacitor-coupled isolators.
What is the function of the NC pin (Pin 6) on SI86S631EC-AS1?
Pin 6 on SI86S631EC-AS1 is marked NC (No Connect) and is internally unconnected. It must remain unpopulated and unconnected on the PCB. Routing traces or placing vias to this pin violates isolation barrier integrity and voids safety certifications associated with SI86S631EC-AS1.
How does the fail-safe mode work on SI86S631EC-AS1, and how is it configured?
SI86S631EC-AS1 implements a factory-configured default-low fail-safe mode: when VDD1 is unpowered but VDD2 remains active, all B-side outputs are driven low. This behavior is fixed per the "EC" ordering suffix and cannot be changed in-circuit - ensuring predictable safe state during controller-side power loss in gate driver applications.
Can SI86S631EC-AS1 support bidirectional communication across its three channels?
Yes. SI86S631EC-AS1 provides three independent, bidirectional digital isolation channels. Each channel operates symmetrically - signals propagate equally well from A-to-B or B-to-A - enabling flexible use in isolated UART, SPI, or custom serial protocols without direction-control pins or external logic.
SI86S631EC-AS1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Capacitive Coupling
- Type:
- SPI
- Isolated Power:
- Yes
- Number of Channels:
- 3
- Inputs - Side 1/Side 2:
- 2/1
- Channel Type:
- Unidirectional
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 150kV/µs
- Data Rate:
- 150Mbps
- Propagation Delay tpLH / tpHL (Max):
- 42ns, 42ns
- Pulse Width Distortion (Max):
- 2ns
- Rise / Fall Time (Typ):
- 2.5ns, 2.5ns
- Voltage - Supply:
- 2.25V ~ 5.5V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SI86S631EC-AS1 FAQ
1.How can I place an order for SI86S631EC-AS1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI86S631EC-AS1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI86S631EC-AS1 reliable?
The price and inventory of SI86S631EC-AS1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI86S631EC-AS1 is usually 5 days.
3.What payment methods are accepted for SI86S631EC-AS1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI86S631EC-AS1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI86S631EC-AS1?
SI86S631EC-AS1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI86S631EC-AS1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI86S631EC-AS1?
For technical support, including SI86S631EC-AS1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI86S631EC-AS1 requirements.
6.How does Aetrix verify that SI86S631EC-AS1 is sourced from the original manufacturer or authorized distributors?
All SI86S631EC-AS1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI86S631EC-AS1 meets industry standards.
7.What is the process for return or replacement of SI86S631EC-AS1?
All SI86S631EC-AS1 units undergo pre-shipment inspection (PSI). If there is an issue with SI86S631EC-AS1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI86S631EC-AS1 part is unused and in its original packaging.
Return procedure for SI86S631EC-AS1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI86S631EC-AS1 Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
